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Cortex-A8 Technical Reference Manual - ARM Information Center

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End-of-test datalog retrieval<br />

Design for Test<br />

Figure 11-10 shows an example of retrieval of the first failure datalog and the pass/fail status for<br />

every array. This is typically run at the end of testing. You can use bitmap test mode on the<br />

failing arrays.<br />

Be careful not to miss a subsequent failure that might occur near the end of the testing sequence.<br />

For example, if a failure occurs on the last RAM access of the test sequence, then the complete<br />

flag asserts only three at-speed cycles after the fail flag asserts. If the fail flag signal goes<br />

through more external delay than the complete flag, the complete flag might be visible<br />

externally before the fail flag. Before classifying a test as passing, give adequate time after<br />

recognizing the complete flag to ensure that the fail flag does not assert.<br />

CLK<br />

ARESETn<br />

MBISTMODE<br />

MBISTSHIFT<br />

MBISTDSHIFT<br />

MBISTDATAIN<br />

MBISTRUN<br />

MBISTRESULT[2:0]<br />

Bitmap datalog retrieval<br />

b110 bxxx<br />

xx,dlog[lsb] xx,dlog[msb-1] xx,dlog[msb]<br />

Figure 11-10 Timing of MBIST end-of-test datalog retrieval<br />

Figure 11-11 shows an example of the start of a failure datalog retrieval during bitmap mode.<br />

The fail flag remains asserted and no more MBIST testing occurs until the MBISTDSHIFT<br />

signal is asserted, that initiates the serial shift-out of the bitmap datalog. This provides time to<br />

switch from fast to slow clocking required for shifting.<br />

PLL glitchless switch between<br />

fast and slow clocking occurs here<br />

CLK<br />

MBISTRESULT[1] (fail flag)<br />

MBISTDSHIFT<br />

MBISTRESULT[0] (data log shift out)<br />

MBISTRUN<br />

Figure 11-11 Timing of MBIST start of bitmap datalog retrieval<br />

Figure 11-12 on page 11-18 shows an example of the end of a failure datalog retrieval during<br />

the execution of a failure bitmap. When all of the bits are shifted out, the PLL switches back to<br />

fast clocking and negates the MBISTDSHIFT signal. This causes the MBIST controller to<br />

resume testing.<br />

<strong>ARM</strong> DDI 0344K Copyright © 2006-2010 <strong>ARM</strong> Limited. All rights reserved. 11-17<br />

ID060510 Non-Confidential<br />

D[lsb]

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