Cortex-A8 Technical Reference Manual - ARM Information Center

12.5.9 Lock Status Register
Debug
31 0
Lock access control
Figure 12-25 Lock Access Register format
Table 12-40 shows how the bit values correspond with the Lock Access Register functions.
Bits Field Function
Note
You can only access the Lock Access Register when the PADDR31 input is LOW. Writes are
ignored when PADDR31 is HIGH.
The Lock Status Register is a read-only register that returns the current lock status of the debug
registers.
Figure 12-26 shows the bit arrangement of the Lock Status Register.
Table 12-40 Lock Access Register bit functions
[31:0] Lock access control Lock access control. To unlock the debug registers, write a 0xC5ACCE55 key to this
register. To lock the debug registers, write any other value. Accesses to locked debug
registers are ignored.
31 3 2 1 0
Reserved
32-bit access
Locked bit
Lock implemented bit
Figure 12-26 Lock Status Register format
Table 12-41 shows how the bit values correspond with the Lock Status Register functions.
Bits Field Function
[31:3] - RAZ.
Table 12-41 Lock Status Register bit functions
[2] 32-bit access 32-bit access. Indicates that a 32-bit access is required to write the key to the Lock
Access Register. This bit always reads 0.
[1] Locked bit Locked bit:
0 = writes are permitted
1 = writes are ignored, reset value.
[0] Lock implemented bit Lock implemented bit. Indicates that the lock functionality is implemented. This bit
always reads 1.
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