Cortex-A8 Technical Reference Manual - ARM Information Center

A.1 AXI interface
Signal Descriptions
For complete descriptions of AXI interface signals, see the AMBA AXI Protocol Specification.
Table A-1 shows the AXI interface signals that have been added or that have different
definitions for the Cortex-A8 processor.
Signal I/O Reset Description
A64n128 I - Statically selects 64-bit or 128-bit AXI bus width:
0 = 128-bit bus width
1 = 64-bit bus width.
This pin is only sampled during reset of the processor.
Table A-1 AXI interface
ACLKEN I - AXI clock gate enable:
0 = AXI clock disabled
1 = AXI clock enabled.
Note
The rising edge of the internal ACLK signal comes two CLK cycles after the
CLK cycle in which ACLKEN is asserted. See Chapter 10 Clock, Reset, and
Power Control.
ARCACHE[3:0]
and
AWCACHE[3:0]
O Undefined Read or write cache type:
b0000 = strongly ordered
b0001 = device
b0010 = reserved
b0011 = normal noncacheable
b0100 and b0101 = reserved
b0110 = cacheable write-through, allocate on reads only
b0111 = cacheable write-back, allocate on reads only
b1000 to b1110 = reserved
b1111 = cacheable write-back, allocate on both reads and writes.
ARM DDI 0344K Copyright © 2006-2010 ARM Limited. All rights reserved. A-2
ID060510 Non-Confidential