Cortex-A8 Technical Reference Manual - ARM Information Center

Table 15-10 shows how the bit values correspond with these registers.
Bits Field Function
[31:4] - Reserved. RAZ, SBZ.
15.6.8 CTI Trigger In Status Register, CTITRIGINSTATUS
Cross Trigger Interface
CTITRIGINSTATUS is a read-only register that provides the status of the CTITRIGIN inputs.
Figure 15-11 shows the bit arrangement of the CTITRIGINSTATUS Register.
Figure 15-11 CTI Trigger In Status Register format
Table 15-11 shows how the bit values correspond with the CTITRIGINSTATUS Register
functions.
15.6.9 CTI Trigger Out Status Register, CTITRIGOUTSTATUS
Table 15-10 CTI Channel to Trigger Enable Registers bit functions
[3:0] TRIGOUTEN Enables a channel event for the corresponding channel to generate an CTITRIGOUT output:
0 = the channel input CTICHIN from the CTM is not routed to the CTITRIGOUT output
1 = the channel input CTICHIN from the CTM is routed to the CTITRIGOUT output.
There is one bit of the register for each of the four channels. For example, enabling bit [0] in
Register CTIOUTEN0, enables CTICHIN[0] to cause a trigger event on the
CTITRIGOUT[0] output.
31 9 8
0
Bits Field Function
[31:9] - Reserved, RAZ.
Reserved TRIGINSTATUS
Table 15-11 CTI Trigger In Status Register bit functions
[8:0] TRIGINSTATUS Displays the status of the CTITRIGIN inputs:
0 = CTITRIGIN is inactive
1 = CTITRIGIN is active.
Because the register provides a view of the raw CTITRIGIN inputs, the reset value is
unknown. There is one bit of the register for each trigger input.
CTITRIGOUTSTATUS is a read-only register that provides the status of the CTITRIGOUT
outputs.
Figure 15-12 shows the bit arrangement of the CTITRIGOUTSTATUS Register.
31 9 8
0
Reserved
TRIGOUTSTATUS
Figure 15-12 CTI Trigger Out Status Register format
ARM DDI 0344K Copyright © 2006-2010 ARM Limited. All rights reserved. 15-15
ID060510 Non-Confidential