Cortex-A8 Technical Reference Manual - ARM Information Center

Value Description
0x60-0x6F Reserved.
0x70 Counts any event from external input source PMUEXTIN[0].
0x71 Counts any event from external input source PMUEXTIN[1].
0x72 Counts any event from both external input sources PMUEXTIN[0] and PMUEXTIN[1].
0x73-0xFF Reserved.
System Control Coprocessor
If this unit generates an interrupt, the processor asserts the pin nPMUIRQ. You can route this
pin to an external interrupt controller for prioritization and masking. This is the only mechanism
that signals this interrupt to the core.
The absolute counts recorded might vary because of pipeline effects. This has negligible effect
except in cases where the counters are enabled for a very short time.
In addition to the counters within the processor, most of the events that Table 3-97 on page 3-85
shows are available to the ETM unit or other external trace hardware to enable the events to be
monitored. See Chapter 14 Embedded Trace Macrocell and Chapter 15 Cross Trigger Interface
for more information.
3.2.50 c9, Performance Monitor Count Registers
EN b
There are four Performance Monitor CouNT (PMCNT0-PMCNT3) Registers in the processor.
The purpose of each PMCNT Register, as selected by the PMNXSEL Register, is to count
instances of an event selected by the EVTSEL Register. Bits [31:0] of each PMCNT Register
contain an event count.
The PMCNT0-PMCNT3 Registers are:
• read/write registers common to Secure and Nonsecure states
• accessible as determined by c9, User Enable Register on page 3-89.
Table 3-98 shows the results of attempted access for each mode.
To access the PMCNT Registers, read or write CP15 with:
MRC p15, 0, , c9, c13, 2; Read PMCNT0-PMCNT3 Registers
MCR p15, 0, , c9, c13, 2; Write PMCNT0-PMCNT3 Registers
Table 3-97 Values for predefined events (continued)
Table 3-98 Results of access to the Performance Monitor Count Registers a
Secure privileged Nonsecure privileged Secure User Nonsecure User
Read Write Read Write Read Write Read Write
0 Data Data Data Data Undefined Undefined Undefined Undefined
1 Data Data Data Data Data Data Data Data
a. An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessor
instruction is executed.
b. The EN bit in c9, User Enable Register on page 3-89 enables User mode access of the Performance Monitor Registers.
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