Cortex-A8 Technical Reference Manual - ARM Information Center

TLB ATTR array examples
To write one entry in data side TLB ATTR array, for example:
LDR R0, =0x252E;
MCR p15, 0, R0, c15, c0, 0; Move R0 to D-L1 Data 0 Register
LDR R1, =0x00C00000;
MCR p15, 0, R1, c15, c0, 3; Write D-L1 Data 0 Register to D-TLB ATTR
To read one entry in data side TLB ATTR array, for example:
System Control Coprocessor
LDR R1, =0x00C00000;
MCR p15, 0, R1, c15, c2, 3; Read D-TLB ATTR into data L1 Data 0 Register
MRC p15, 0, R0, c15, c0, 0; Move D-L1 Data 0 Register to R0
To write one entry in instruction side TLB ATTR array, for example:
LDR R0, =0x252E;
MCR p15, 0, R0, c15, c1, 0; Move R0 to I-L1 Data 0 Register
LDR R1, =0x00C00000;
MCR p15, 0, R1, c15, c1, 3; Write I-L1 Data 0 Register to I-TLB ATTR
To read one entry in instruction side TLB ATTR array, for example:
LDR R1, =0x00C00000;
MCR p15, 0, R1, c15, c3, 3; Read I-TLB ATTR into data L1 Data 0 Register
MRC p15, 0, R0, c15, c0, 0; Move I-L1 Data 0 Register to R0
TLB PA array examples
3.2.76 c15, L1 HVAB array operations
To write one entry in data side TLB PA array, for example:
LDR R0, =0x05730000;
MCR p15, 0, R0, c15, c0, 0; Move R0 to D-L1 Data 0 Register
LDR R1, =0x00C00000;
MCR p15, 0, R1, c15, c0, 4; Write D-L1 Data 0 Register to D-TLB PA
To read one entry in data side TLB PA array, for example:
LDR R1, =0x00C00000;
MCR p15, 0, R1, c15, c2, 4; Read D-TLB PA into data L1 Data 0 Register
MRC p15, 0, R0, c15, c0, 0; Move D-L1 Data 0 Register to R0
To write one entry in instruction side TLB PA array, for example:
LDR R0, =0x05730000;
MCR p15, 0, R0, c15, c1, 0; Move R0 to I-L1 Data 0 Register
LDR R1, =0x00C00000;
MCR p15, 0, R1, c15, c1, 4; Write I-L1 Data 0 Register to I-TLB PA
To read one entry in instruction side TLB PA array, for example:
LDR R1, =0x00C00000;
MCR p15, 0, R1, c15, c3, 4; Read I-TLB PA into data L1 Data 0 Register
MRC p15, 0, R0, c15, c1, 0; Move I-L1 Data 0 Register to R0
The purpose of the L1 HVAB array operations is to:
• read the L1 HVAB array contents and write to the system debug data registers
• write into the system debug data registers and into the L1 HVAB array.
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