Cortex-A8 Technical Reference Manual - ARM Information Center

3.2.79 c15, BTB array operations
Address
Reserved
To write one entry in instruction side L1 data array, for example:
System Control Coprocessor
LDR R0, =0x01234567;
MCR p15, 0, R0, c15, c1, 0; Move R0 to I-L1 Data 0 Register
LDR R2, =0x1B;
MCR p15, 0, R2, c15, c1, 1; Move R0 to I-L1 Data 1 Register
LDR R1, =0x800000D8;
MCR p15, 0, R1, c15, c1, 7; Write I-L1 Data 0 or 1 Register to I-L1 data
To read one entry in instruction side L1 data array, for example:
LDR R1, =0x800000D8;
MCR p15, 0, R1, c15, c3, 7; Read I-L1 data into I-L1 Data 0 or 1 Register
MRC p15, 0, R0, c15, c1, 0; Move I-L1 Data 0 Register to R0
MRC p15, 0, R2, c15, c1, 1; Move I-L1 Data 1 Register to R2
Note
The granularity of the dirty bits is so that two sets of dirty bits are updated for each CP15 L1
DATA array write operation. A doubleword set of dirty bits are updated so that if word 0 or word
1 is being updated, then the D-bit and D-bit parity bits are updated for both word 0 and word 1.
The purpose of the Branch Target Buffer (BTB) array operations is to:
• read the BTB array contents and write into the system debug data registers
• write into the system debug data registers and into the BTB array.
The BTB array operation is accessible in secure privileged modes only.
Figure 3-77 shows the bit arrangement of the BTB array read operation.
31 30 29 11 10
3 2 0
Reserved Address
Address
Reserved
Figure 3-77 BTB array read operation format
Figure 3-78 on page 3-135 shows the bit arrangement of the BTB array write operation.
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BTB
array