Cortex-A8 Technical Reference Manual - ARM Information Center

CSSR Size
3.2.24 c0, Cache Size Selection Register
Table 3-43 shows the results of attempted access for each mode.
To access the Cache Size Identification Register, read CP15 with:
MRC p15, 1, , c0, c0, 0; Cache Size Identification Register
System Control Coprocessor
Table 3-42 Encodings of the Cache Size Identification Register (continued)
Complete
register
encoding
0x2 0KB 0xF0000000 1 1 1 1 0x0000 0x0 0x0
128KB 0xF01FE03A 1 1 1 1 0x00FF 0x7 0x2
256KB 0xF03FE03A 1 1 1 1 0x01FF 0x7 0x2
512KB 0xF07FE03A 1 1 1 1 0x03FF 0x7 0x2
1024KB 0xF0FFE03A 1 1 1 1 0x07FF 0x7 0x2
0x3-0xF - 0x0 Reserved
Register bit field encoding
WT WB RA WA NumSets Associativity LineSize
Table 3-43 Results of access to the Cache Size Identification Register a
Secure privileged Nonsecure privileged Secure User Nonsecure User
Read Write Read Write Read Write Read Write
Data Undefined Data Undefined Undefined Undefined Undefined Undefined
a. An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessor
instruction is executed.
The purpose of the Cache Size Selection Register is to hold the value that the processor uses to
select the Cache Size Identification Register to use.
The Cache Size Selection Register is:
• a read/write register banked for Secure and Nonsecure states
• accessible in privileged modes only.
Figure 3-19 shows the bit arrangement of the Cache Size Selection Register.
31
4 3 1 0
Reserved Level
Figure 3-19 Cache Size Selection Register format
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