Cortex-A8 Technical Reference Manual - ARM Information Center

Bits Field Function
[13] Execute
instruction
enable
[12] CP14 user
access disable
[11] Interrupt
disable
Debug
Execute ARM instruction enable bit. This is a read/write bit.
0 = disabled, reset value
1 = enabled.
If this bit is set to 1 and an ITR write succeeds, the processor fetches an instruction from the
ITR for execution. If this bit is set to 1 when the processor is not in debug state, the behavior
of the processor is Unpredictable.
CP14 debug user access disable control bit. This is a read/write bit.
0 = CP14 debug user access enable, reset value
1 = CP14 debug user access disable.
If this bit is set to 1 and a User mode process tries to access any CP14 debug registers, the
Undefined Instruction exception is taken.
Interrupts disable bit. This is a read/write bit.
0 = interrupts enabled, reset value
1 = interrupts disabled.
If this bit is set to 1, the IRQ and FIQ input signals are disabled. The external debugger can
set this bit to 1 before it executes code in normal state as part of the debugging process. If
this bit is set to 1, an interrupt does not take control of the program flow. For example, the
debugger might use this bit to execute an OS service routine to bring a page from disk into
memory. It might be undesirable to service any interrupt during the routine execution.
[10] DbgAck Debug Acknowledge bit. This is a read/write bit. If this bit is set to 1, both the DBGACK
and DBGTRIGGER output signals are forced HIGH, regardless of the processor state. The
external debugger can use this bit if it wants the system to behave as if the processor is in
debug state. Some systems rely on DBGACK to determine whether the application or
debugger generates the data accesses. The reset value is 0.
[9] - Reserved. UNP, SBZ.
[8] Sticky
Undefined
[7] Sticky
imprecise
abort
[6] Sticky precise
abort
Table 12-14 Debug Status and Control Register bit functions (continued)
Sticky Undefined bit:
0 = No Undefined Instruction exception occurred in debug state since the last time this bit
was cleared. This is the reset value.
1 = An Undefined Instruction exception has occurred while in debug state since the last time
this bit was cleared.
This flag detects Undefined instruction exceptions generated by instructions issued to the
processor through the ITR. This bit is set to 1 when an Undefined Instruction exception
occurs while the processor is in debug state. Writing a 1 to DRCR[2] clears this bit to 0. See
Debug Run Control Register on page 12-26.
Sticky imprecise Data Abort bit:
0 = no imprecise Data Aborts occurred since the last time this bit was cleared, reset value
1 = an imprecise Data Abort occurred since the last time this bit was cleared.
This flag detects imprecise Data Aborts triggered by instructions issued to the processor
through the ITR. This bit is set to 1 when an imprecise Data Abort occurs while the processor
is in debug state. Writing a 1 to DRCR[2] clears this bit to 0. See Debug Run Control Register
on page 12-26.
Sticky precise Data Abort bit:
0 = no precise Data Abort occurred since the last time this bit was cleared, reset value
1 = a precise Data Abort occurred since the last time this bit was cleared.
This flag detects precise Data Aborts generated by instructions issued to the processor
through the ITR. This bit is set to 1 when a precise Data Abort occurs while the processor is
in debug state. Writing a 1 to DRCR[2] clears this bit to 0. See Debug Run Control Register
on page 12-26.
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