Cortex-A8 Technical Reference Manual - ARM Information Center

9.3 AXI instruction transactions
9.3.1 AXI instruction address transactions
External Memory Interface
This section describes the AXI master interface behavior for instruction side transactions to
either Cacheable or Noncacheable regions of memory.
See the AMBA AXI Protocol Specification for details of the other AXI signals.
Table 9-5 shows the values of ARADDR[31:0], ARLEN[3:0], ARSIZE[2:0],
ARBURST[1:0], and ARLOCK[1:0] for instruction transactions.
Transfer Bus width ARADDR
[31:0] a
MMU translation table
translation table walk b
Table 9-5 AXI address channel for instruction transactions
ARLEN
[3:0]
ARSIZE
[2:0]
ARBURST[
1:0]
ARLOCK
[1:0]
64 [31:6]bbbb00 0 32-bit Incr Normal
128 [31:6]bbbb00 0 32-bit Incr Normal
Noncacheable 64 [31:6]bbb000 0-7 64-bit Incr Normal
128 [31:6]bb0000 0-3 128-bit Incr Normal
Cacheable linefill 64 [31:6]bbb000 7 64-bit Wrap Normal
128 [31:6]bb0000 3 128-bit Wrap Normal
a. ARADDR[31:0] is a 32-bit signal with bits [5:3] set to any value and bits [2:0] set to 0, unless otherwise indicated.
This determines the ARLEN[3:0] value depending on the transfer type and bus width. For example, a noncacheable
instruction fetch with ARADDR[5:0] = b101000 for a 64-bit bus width, results in an ARLEN[3:0] = b0010. In this
example, doublewords 5, 6, and 7 of the cache line are transferred.
b. This is for noncacheable or strongly ordered table walk only. For cacheable table walk, the bus transaction is a
cacheable linefill.
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