Cortex-A8 Technical Reference Manual - ARM Information Center

10.2.5 Reset of memory arrays
Clock, Reset, and Power Control
background and does not interfere with reset code. Any attempt to enable the L2 unified cache
or perform any L2 cache maintenance operations stalls the processor until the hardware reset is
complete.
The processor has two pins, L1RSTDISABLE and L2RSTDISABLE, to control the hardware
reset process. The usage models of the hardware reset pins are as follows:
1. For applications that do not retain the L1 data cache and L2 unified cache RAM contents
throughout a core power-down sequence, the hardware resets both the L1 data cache and
L2 unified cache at every reset, using ARESETn or nPORESET. Both
L1RSTDISABLE and L2RSTDISABLE must be tied LOW. This is the recommended
usage model.
2. For applications that do retain the L1 data cache or L2 unified cache RAM contents
throughout a core power-down sequence, hardware must control both the
L1RSTDISABLE and L2RSTDISABLE signals during reset. When the system is
powering up for the first time, the hardware reset signals, L1RSTDISABLE and
L2RSTDISABLE, must be tied LOW to invalidate both the L1 data cache and L2 unified
cache RAM contents using the hardware reset mechanism. If either the L1 data cache or
L2 unified cache must retain its data during a reset sequence, then the corresponding
hardware reset disable must be tied HIGH.
3. If the hardware array reset mechanism is not used, then both the L1RSTDISABLE and
L2RSTDISABLE pins must be tied HIGH.
Both the L1RSTDISABLE and L2RSTDISABLE pins must be valid at least 16 CLK cycles
before and after the deasserting edge of ARESETn and nPORESET.
During reset of the processor, the following memory arrays are invalidated at reset:
• branch prediction arrays (BTB and GHB)
• L1 instruction and data TLBs
• L1 data cache valid RAM, if L1RSTDISABLE is tied LOW
• L2 unified cache valid RAM, if L2RSTDISABLE is tied LOW.
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