Cortex-A8 Technical Reference Manual - ARM Information Center

System Control Coprocessor
— the privileged only Thread and Process ID Register is only accessible in privileged
modes, and is read/write.
Table 3-146 shows the results of attempted access to each register for each mode.
To access the Thread and Process ID Registers, read or write CP15 with:
MRC p15, 0, , c13, c0, 2 ; Read User read/write Thread and Process ID Register
MCR p15, 0, , c13, c0, 2 ; Write User read/write Thread and Process ID Register
MRC p15, 0, , c13, c0, 3 ; Read User read-only Thread and Process ID Register
MCR p15, 0, , c13, c0, 3 ; Write User read-only Thread and Process ID Register
MRC p15, 0, , c13, c0, 4 ; Read Privileged only Thread and Process ID Register
MCR p15, 0, , c13, c0, 4 ; Write Privileged only Thread and Process ID Register
Reading or writing the Thread and Process ID Registers has no effect on the processor state or
operation. These registers provide OS support and must be managed by the OS.
You must clear the contents of all Thread and Process ID Registers on process switches to
prevent data leaking from one process to another. This is important to ensure the security of
secure data.
3.2.74 c15, L1 system array debug data registers
Table 3-146 Results of access to the Thread and Process ID Registers a
Secure
privileged Nonsecure privileged Secure User Nonsecure User
Register b Read Write Read Write Read Write Read Write
User
read/write
User
read-only
Privileged
only
Secure
data
Secure
data
Secure
data
Secure
data
Secure
data
Secure
data
Nonsecure
data
Nonsecure
data
Nonsecure
data
Nonsecure
data
Nonsecure
data
Nonsecure
data
Secure
data
Secure
data
The purpose of the L1 system array debug data registers is to hold the data:
• that is returned on instruction side or data side TLB CAM, TLB ATTR, TLB PA, HVAB,
tag, data, GHB, and BTB instruction or data side read operations
• for TLB CAM, TLB ATTR, TLB PA, HVAB, tag, data, GHB, and BTB instruction side
or data side write operations.
Because BTB, TLB, and data arrays are greater than 32-bits wide, the processor contains two
registers, data low register and data high register, to hold data when retrieving or registering data
as a result of read/write operations. If the data is greater than 32-bit wide, both the low and high
registers are used to transfer data. Otherwise, only the low register is used to transfer data.
The Data 0 and Data 1 read/write registers are accessible in secure privileged modes only.
To access the L1 system debug registers, read or write CP15 with:
MCR p15, 0, , c15, c0, 0 ; Write data L1 Data 0 Register
Secure data Nonsecure
data
Undefined Nonsecure
data
Nonsecure
data
Undefined
Undefined Undefined Undefined Undefined
a. An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessor
instruction is executed.
b. Each row refers to a Thread and Process ID Register. For example, the User read/write row refers to the User read/write
Thread and Process ID Register.
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