Cortex-A8 Technical Reference Manual - ARM Information Center

Bits Field Function
[8:5] Byte address
select
Debug
Byte address select. For breakpoints programmed to match an IVA, you must write a
word-aligned address to the BVR. You can then use this field to program the breakpoint so
it hits only if you access certain byte addresses.
If you program the BRP for IVA match:
b0000 = the breakpoint never hits
b0011 = the breakpoint hits if any of the two bytes starting at address BVR & 0xFFFFFFFC +0
is accessed
b1100 = the breakpoint hits if any of the two bytes starting at address BVR & 0xFFFFFFFC +2
is accessed
b1111 = the breakpoint hits if any of the four bytes starting at address BVR & 0xFFFFFFFC +0
is accessed.
If you program the BRP for IVA mismatch, the breakpoint hits where the corresponding IVA
breakpoint does not hit, that is, the range of addresses covered by an IVA mismatch
breakpoint is the negative image of the corresponding IVA breakpoint.
If you program the BRP for context ID comparison, this field must be set to b1111.
Otherwise, breakpoint and watchpoint debug events might not be generated as expected.
Note
[4:3] - Reserved. RAZ, SBZP.
Writing a value to BCR[8:5] where BCR[8] is not equal to BCR[7], or BCR[6] is not equal
to BCR[5], has Unpredictable results.
[2:1] S Supervisor access control. The breakpoint can be conditioned on the mode of the processor:
b00 = User, System, or Supervisor
b01 = privileged
b10 = User
b11 = any.
[0] B Breakpoint enable:
0 = breakpoint disabled, reset value
1 = breakpoint enabled.
a. If BCR[28:24] is not set to b00000, then BCR[8:5] must be set to b1111. Otherwise, the behavior is Unpredictable. In addition,
if BCR[28:24] is not set to b00000, then the corresponding BVR bits that are not being included in the comparison
Should-Be-Zero. Otherwise, the behavior is Unpredictable. If you program this BRP for context ID comparison, you must set
this field to b00000. Otherwise, the behavior is Unpredictable. There is no encoding for a full 32-bit mask but you can achieve
the same effect of a break anywhere breakpoint by setting BCR[22] to 1 and BCR[8:5] to b0000.
BVR[22:20] Meaning
Table 12-23 Breakpoint Control Registers bit functions (continued)
Table 12-24 Meaning of BVR bits [22:20]
b000 The corresponding BVR[31:2] is compared against the IVA bus and the state of the processor against this
BCR. It generates a breakpoint debug event on a joint IVA and state match.
b001 The corresponding BVR[31:2] is compared against the IVA bus and the state of the processor against this
BCR. This BRP is linked with the one indicated by BCR[19:16] linked BRP field. They generate a
breakpoint debug event on a joint IVA, context ID, and state match.
b010 The corresponding BVR[31:0] is compared against CP15 Context ID Register, c13 and the state of the
processor against this BCR. This BRP is not linked with any other one. It generates a breakpoint debug
event on a joint context ID and state match. For this BRP, BCR[8:5] must be set to b1111. Otherwise, it
is Unpredictable whether a breakpoint debug event is generated.
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