Cortex-A8 Technical Reference Manual - ARM Information Center

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16.8 Scheduling example Instruction Cycle Timing Example 16-6 shows a sample code segment and how the processor might schedule it. Example 16-6 Dual issue instruction sequence for integer pipeline Cycle PC Opcode Instruction Timing description 1 0x00000ed0: 0xe12fff1e BX r14 Dual issue pipeline 0 1 0x00000ee4: 0xe3500000 CMP r0,#0 Dual issue in pipeline 1 2 0x00000ee8: 0xe3a03003 MOV r3,#3 Dual issue pipeline 0 2 0x00000eec: 0xe3a00000 MOV r0,#0 Dual issue in pipeline 1 3 0x00000ef0: 0x05813000 STREQ r3,[r1,#0] Dual issue in pipeline 0, r3 not needed until E3 3 0x00000ef4: 0xe3520004 CMP r2,#4 Dual issue in pipeline 1 4 0x00000ef8: 0x979ff102 LDRLS pc,[pc,r2,LSL #2] Single issue pipeline 0, +1 cycle for load to pc, no extra cycle for shift since LSL #2 5 0x00000f2c: 0xe3a00001 MOV r0,#1 Dual issue with 2nd iteration of load in pipeline 1 6 0x00000f30: 0xea000000 B {pc}+8 #0xf38 dual issue pipeline 0 6 0x00000f38: 0xe5810000 STR r0,[r1,#0] Dual issue pipeline 1 7 0x00000f3c: 0xe49df004 LDR pc,[r13],#4 Single issue pipeline 0, +1 cycle for load to pc 8 0x0000017c: 0xe284200c ADD r2,r4,#0xc Dual issue with 2nd iteration of load in pipeline 1 9 0x00000180: 0xe5960004 LDR r0,[r6,#4] Dual issue pipeline 0 9 0x00000184: 0xe3a0100a MOV r1,#0xa Dual issue pipeline 1 12 0x00000188: 0xe5900000 LDR r0,[r0,#0] Single issue pipeline 0: r0 produced in E3, required in E1, so +2 cycle stall 13 0x0000018c: 0xe5840000 STR r0,[r4,#0] Single issue pipeline 0 due to LS resource hazard, no extra delay for r0 since produced in E3 and consumed in E3 14 0x00000190: 0xe594000c LDR r0,[r4,#0xc] Single issue pipeline 0 due to LS resource hazard 15 0x00000194: 0xe8bd4070 LDMFD r13!,{r4-r6,r14} Load multiple loads r4 in 1st cycle, r5 and r6 in 2nd cycle, r14 in 3rd cycle, 3 cycles total 17 0x00000198: 0xea000368 B {pc}+0xda8 #0xf40 dual issue in pipeline 1 with 3rd cycle of LDM 18 0x00000f40: 0xe2800002 ADD r0,r0,#2 ARM Single issue in pipeline 0 19 0x00000f44: 0xe0810000 ADD r0,r1,r0 ARM Single issue in pipeline 0, no dual issue due to hazard on r0 produced in E2 and required in E2 Example 16-7 shows a sample instruction sequence for the NEON pipeline. Example 16-7 Instruction sequence for the NEON pipeline Cycle PC Opcode Instruction Timing description 1 0x00003690: 0xf2dbeac8 VMULL.S16 q15,d27,d0[1] ;4X16 SIMD multiply 2 0x00003694: 0xf2daaac8 VMULL.S16 q13,d26,d0[1] ;independent from previous multiply, issued in back-to-back cycles 2 0x00003698: 0xf4402a5d VST1.16 {d18,d19},[r0@64]! ;128bit 2-issue cycle store (1st issue cycle is dual issued with previous instruction) 3 0x0000369c: 0xf2d7685a VRSHRN.I32 d22,q5,#9 ;shift operation (dual issued with 2nd issue cycle of previous store) 4 0x000036a0: 0xf2d7785c VRSHRN.I32 d23,q6,#9 ;independent from previous shift, executed in back-to-back cycles 5 0x000036a4: 0xf29caac0 VMULL.S16 q5,d28,d0[0] ;4X16 SIMD multiply 6 0x000036a8: 0xf29dcac0 VMULL.S16 q6,d29,d0[0] ;independent from previous multiply, issued in back-to-back cycles 7 0x000036ac: 0xf26aa8c6 VADD.I32 q13,q13,q3 ;4x32 (128bit) VADD uses result of multiply from cycle 2. 8 0x000036b0: 0xf26ee8c8 VADD.I32 q15,q15,q4 ;4x32 (128bit) independent from previous add, issued in back-to-back cycles 9 0x000036b4: 0xf29e6260 VMLAL.S16 q3,d14,d0[2] ;independent multiply 9 0x000036bc: 0xf4004a5d VST1.16 {d4,d5},[r0@64]! ;128bit 2-issue cycle store (1st issue cycle ARM DDI 0344K Copyright © 2006-2010 ARM Limited. All rights reserved. 16-37 ID060510 Non-Confidential
is dual issued with previous instruction) 10 0x000036c0: 0xf2d7a87a VRSHRN.I32 d26,q13,#9 ;shift operation (dual issued with 2nd issue cycle of previous store) Example 16-8 shows an instruction sequence for the VFP pipeline. Instruction Cycle Timing Example 16-8 Instruction sequence for VFP pipeline Cycle PC Opcode Instruction Timing description 4 0x00002c44: 0xeeb01a49 FCPYS s2,s18 ;4 cycle single precision register move 8 0x00002c48: 0xeef00a68 FCPYS s1,s17 ;4 cycle single precision register move 12 0x00002c4c: 0xeeb00a48 FCPYS s0,s16 ;4 cycle single precision register move 12 0x00002c50: 0xeb000116 BL {pc}+0x460 ;branch executed ‘for free’ in ARM pipeline, not seen by Neon 19 0x000030b0: 0xee200a21 FMULS s0,s0,s3 ;7 cycle single precision multiply operation 30 0x000030b4: 0xee000a82 FMACS s0,s1,s4 ;11 cycle single precision multiply accumulate (uses NFP multiply and add pipelines with bypassing of add format stage) 41 0x000030b8: 0xee010a22 FMACS s0,s2,s5 ;11 cycle single precision multiply accumulate (uses NFP multiply and add pipelines with bypassing of add format stage) 41 0x000030bc: 0xe12fff1e BX lr ;branch executed ‘for free’ in ARM pipeline, not seen by Neon 45 0x00002c54: 0xeeb01a4a FCPYS s2,s20 ;4 cycle single precision register move 80 0x00002c58: 0xeeb10ac0 FSQRTS s0,s0 ;35 cycles to execute single precision square root function (number of cycles is data dependent) 112 0x00002c5c: 0xeec10a00 FDIVS s1,s2,s0 ;32 cycles to execute single precision divide function (number of cycles is data dependent) 116 0x00002c60: 0xeeb00a69 FCPYS s0,s19 ;4 cycle single precision register move 123 0x00002c64: 0xee600a20 FMULS s1,s0,s1 ;7 cycle single precision multiply operation ARM DDI 0344K Copyright © 2006-2010 ARM Limited. All rights reserved. 16-38 ID060510 Non-Confidential
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Copyright © 2006-2010 ARM Limited.
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Web Address http://www.arm.com ARM
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Contents 2.14 The program status re
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Contents 16.6 Instruction-specific
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List of Tables Table 3-16 Debug Fea
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List of Tables Table 3-136 Secure o
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List of Tables Table 12-59 Values t
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List of Figures Cortex-A8 Technical
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List of Figures Figure 3-77 BTB arr
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List of Figures Figure 15-16 CTI Ch
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About this manual Product revision
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old Highlights interface elements,
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Feedback Feedback on the product Fe
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1.1 About the processor Introductio
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1.3 Components of the processor L1
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1.3.6 NEON 1.3.7 ETM The NEON unit
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1.5 Debug Introduction The processo
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1.7 Configurable options Table 1-1
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Introduction • The various data a
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1.9.6 r2p0-r2p1 1.9.7 r2p1-r2p2 1.9
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Chapter 2 Programmers Model This ch
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2.2 Thumb-2 instruction set Program
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Bits Field Function Programmers Mod
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2.4 Jazelle Extension 2.4.1 Jazelle
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2.5 Security Extensions architectur
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2.6 Advanced SIMD architecture Prog
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2.8 Processor operating states 2.8.
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2.10 Memory formats 2.10.1 Byte-inv
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2.12 Operating modes Programmers Mo
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System and User r0 r1 r2 r3 r4 r5 r
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2.14 The program status registers 2
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2.14.5 The GE[3:0] bits Programmers
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Mode bits Programmers Model M[4:0]
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2.15 Exceptions 2.15.1 Exception en
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2.15.5 Interrupt request 2.15.6 Abo
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This restores both the PC and the C
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2.15.13 Exception priorities Progra
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2.17 Hardware consideration for Sec
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SECMONOUT[78] instruction caches at
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Chapter 3 System Control Coprocesso
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System Control Coprocessor Register
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3.1.3 MMU control and configuration
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3.2 System control coprocessor regi
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CRn Op1 CRm Op2 Register or operati
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3.2.2 c0, Main ID Register System C
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3.2.4 c0, TCM Type Register 3.2.5 c
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3.2.7 c0, Processor Feature Registe
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• accessible in privileged modes
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System Control Coprocessor Table 3-
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Bits Field Function [11:8] L1 Harva
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Bits Field Function [11:8] Harvard
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31 28 27 24 23 20 19 16 15 12 11 8
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Table 3-30 shows the results of att
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System Control Coprocessor 31 28 27
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Table 3-36 shows the results of att
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• accessible in privileged modes
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CSSR Size 3.2.24 c0, Cache Size Sel
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System Control Coprocessor 31 30 29
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MCR p15, 0, , c1, c0, 0 ; Write Con
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Bits Field [19] Clock stop request
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Bits Field Security State NS S Tabl
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3.2.28 c1, Secure Configuration Reg
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AW EA Function Table 3-55 shows the
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3.2.32 c2, Translation Table Base R
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System Control Coprocessor Figure 3
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Bits Field Function 3.2.35 c5, Data
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3.2.36 c5, Instruction Fault Status
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3.2.38 c6, Data Fault Address Regis
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System Control Coprocessor Note •
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System Control Coprocessor Figure 3
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3.2.41 c8, TLB operations The data
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Figure 3-38 shows the bit arrangeme
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EN b 3.2.44 c9, Count Enable Clear
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EN b 3.2.46 c9, Software Increment
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EN b 3.2.48 c9, Cycle Count Registe
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EN b Table 3-96 shows the results o
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Value Description 0x44 Any cacheabl
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DBGEN || NIDEN 3.2.51 c9, User Enab
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EN 3.2.53 c9, Interrupt Enable Clea
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Figure 3-48 shows the bit arrangeme
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3.2.55 c9, L2 Cache Auxiliary Contr
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Bits Field Function [8:6] Tag RAM l
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TL bit value 3.2.57 c10, TLB preloa
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The PLE Identification and Status R
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3.2.62 c11, PLE enable commands U b
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Bits Field Function System Control
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U bit PLE bit Table 3-129 shows the
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U bit PLE bit System Control Coproc
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3.2.68 c12, Secure or Nonsecure Vec
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3.2.70 c12, Interrupt Status Regist
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The FCSE PID Register is: • a rea
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TLB CAM read/write TLB ATTR read/wr
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MCR p15 0, , c15, c3, 4 ; I-L1 TLB
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31 27 26 22 21 0 Reserved L1 Data 0
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System Control Coprocessor The L1 H
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3.2.78 c15, L1 data array operation
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Instruction L1 Data 0 register Inst
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Parity/ECC RAM read/write Data RAM
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3.2.82 c15, L2 parity/ECC array ope
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3.2.84 c15, L2 data array operation
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4.1 About unaligned and mixed-endia
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Unaligned Data and Mixed-endian Dat
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Chapter 5 Program Flow Prediction T
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5.2 Predicted instructions Program
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Program Flow Prediction Because ret
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5.4 Guidelines for optimal performa
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5.6 Operating system and predictor
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6.1 About the MMU Memory Management
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6.3 16MB supersection support Memor
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6.5 External aborts 6.5.1 External
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6.7 MMU software-accessible registe
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7.1 About the L1 memory system Leve
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7.2.6 Instruction cache maintenance
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L1 inner policy a L2 outer policy N
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7.5 Data cache features 7.5.1 Data
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7.7 Hardware support for virtual al
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Chapter 8 Level 2 Memory System Thi
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8.2 Cache organization 8.2.1 L2 cac
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8.3 Enabling and disabling the L2 c
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Level 2 Memory System Note It is en
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Level 2 Memory System Note You must
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Lock address : LockAddr Lock free :
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8.7 Parity and error correction cod
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9.1 About the external memory inter
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Integer data and CP14 writes Noncac
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9.4 AXI data read/write transaction
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Noncacheable, or strongly ordered,
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Noncacheable store word Noncacheabl
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LA Last Access External Memory Inte
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10.1 Clock domains 10.1.1 AXI clock
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10.2 Reset domains 10.2.1 Power-on
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REFCLK (PLL input) nPORESET ARESETn
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10.3 Power control 10.3.1 Dynamic p
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Clock, Reset, and Power Control the
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ATB APB I/O clamp I/O clamp L/S = L
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ATB APB I/O clamp I/O clamp LS = Le
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Clock, Reset, and Power Control 3.
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Powering up the debug and ETM domai
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7. Perform a normal software reset
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Clock, Reset, and Power Control 5.
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Chapter 11 Design for Test This cha
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In L1 MBIST Instruction Register Fi
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Note Do not test the CAMBIST arrays
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• number of rows of the L2 data,
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Design for Test Not all row setting
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In Design for Test Figure 11-4 show
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Design for Test When testing the ta
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CLK ARESETn MBISTMODE MBISTSHIFT MB
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End-of-test datalog retrieval Desig
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Pattern N RWRXMARCH 8N Row-fast Sta
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4. rscan array, data_seed = invert.
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3. R_, W, R, decr. 4. rscan data fr
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• the data after pass 1 of XADDRB
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(1 + (2 17)) 2 17 = 4,587,520 cycle
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processor input ports WEXTEST WINTE
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Design for Test toggling during shi
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12.1 Debug systems 12.1.1 Debug hos
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12.2.3 Security extensions and debu
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Instruction Mnemonic Description 12
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12.3.6 Power domains and debug 12.3
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Table 12-5 shows the APB interface
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12.4 Debug register descriptions Te
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MRC p14, 0, , c0, c0, 0 ; Read Debu
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31 30 29 28 27 26 25 24 23 22 21 20
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Bits Field Function [21:20] DTR acc
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Bits Field Function To access the D
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12.4.7 Watchpoint Fault Address Reg
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Bits Access Normal address [2] RW V
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12.4.12 Debug Run Control Register
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Table 12-23 shows how the bit value
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BVR[22:20] Meaning b011 The corresp
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Bits Field Function [15:14] Secure
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12.4.18 Operating System Lock Statu
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Debug • The sequence can be aband
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12.5 Management registers Offset Th
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Offset Register number Mnemonic Fun
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Bits Field Function [5] nDMAIRQ nDM
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12.5.7 Claim Tag Clear Register 12.
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12.5.10 Authentication Status Regis
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Table 12-45 shows fields that are i
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12.6 Debug events 12.6.1 Software d
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12.6.5 Watchpoint debug events If a
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Table 12-53 shows the values in the
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12.8 Debug state 12.8.1 Entering de
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12.8.4 Writing to the CPSR in debug
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Mode SCR[0] For CP15 instructions,
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12.8.9 Leaving debug state Imprecis
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12.9.3 Cache usage profiling Debug
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Note DBGPWRDWNREQ must be tied LOW
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If software running on the processo
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Rules for accessing the DCC At the
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} While the processor is running, i
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Debug Table 12-59 Values to write t
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12.11.4 Debug state entry Example 1
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} // Step 1. Update the CPSR value
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Writing the CPSR in debug state Exa
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Debug Example 12-21 Reading a word
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} // Step 9. Check for aborts. abor
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12.12 Debugging systems with energy
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MOV r0, r4 POP {r4, pc} Example 12-
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Chapter 13 NEON and VFP Programmers
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13.2 General-purpose registers 13.2
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13.3 Short vectors 13.3.1 About reg
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13.3.2 Operations using register ba
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NEON and VFP Programmers Model The
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Note All hardware ID information is
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Bits Field Function [12:8] - Reserv
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NEON and VFP Programmers Model Tabl
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13.6 Compliance with the IEEE 754 s
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Underflow NEON and VFP Programmers
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14.1 About the ETM 14.1.1 ETM featu
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14.1.3 NEON Bridge and bus matrix A
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14.3 ETM register summary The ETM r
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Bits Field Function [11:8] Major ET
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14.4.4 Peripheral Identification Re
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See the ETM Architecture Specificat
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Embedded Trace Macrocell Table 14-1
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14.5.3 Enabling events 14.5.4 Addre
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14.7 Context ID tracing Embedded Tr
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14.9 Idle state control Embedded Tr
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Chapter 15 Cross Trigger Interface
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CTICHIN[0] CTICHIN[1] CTICHIN[2] CT
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15.2 Trigger inputs and outputs Tri
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15.3 Connecting asynchronous channe
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15.5 CTI register summary Address o
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15.6 CTI register descriptions This
Page 477 and 478: 15.6.4 CTI Application Trigger Clea
Page 479 and 480: Table 15-10 shows how the bit value
Page 481 and 482: 15.6.12 ASIC Control Register, ASIC
Page 483 and 484: 15.7 CTI Integration Test Registers
Page 485 and 486: 15.7.4 ITTRIGOUTACK, 0xEF0 15.7.5 I
Page 487 and 488: Cross Trigger Interface Table 15-26
Page 489 and 490: 15.8.3 Device Type Identifier, 0xFC
Page 491 and 492: Cross Trigger Interface Table 15-31
Page 493 and 494: 16.1 About instruction cycle timing
Page 495 and 496: Instruction Cycle Timing Example 16
Page 497 and 498: Table 16-4 shows the operation of m
Page 499 and 500: Table 16-9 shows the operation of l
Page 501 and 502: d. See Load/store instructions on p
Page 503 and 504: Instruction Cycle Timing Table 16-1
Page 505 and 506: 16.4 Other pipeline-dependent laten
Page 507 and 508: 16.4.5 Conditional instructions Ins
Page 509 and 510: 16.6 Instruction-specific schedulin
Page 511 and 512: Instruction Cycle Timing VNEG Dd,Dm
Page 513 and 514: VMLA a VMLS a VMLAa VMLSa VQDMLAa V
Page 515 and 516: VSLI VSRI 16.6.5 Advanced SIMD floa
Page 517 and 518: 16.6.6 Advanced SIMD byte permute i
Page 519 and 520: Instruction Table 16-23 shows the o
Page 521 and 522: Instruction VST3 3-reg (unaligned)
Page 523 and 524: Instruction VLD3 3-reg (unaligned)
Page 525 and 526: Instruction Single precision cycles
Page 527: • FMACS, FNMACS • FMSCS, FNMSCS
Page 531 and 532: 17.1 About setup and hold times AC
Page 533 and 534: 17.2 AXI interface Table 17-2 shows
Page 535 and 536: 17.3 ATB and CTI interfaces Table 1
Page 537 and 538: AC Characteristics Table 17-4 Timin
Page 539 and 540: 17.6 L2 preload interface AC Charac
Page 541 and 542: 17.8 Miscellaneous signals AC Chara
Page 543 and 544: A.1 AXI interface Signal Descriptio
Page 545 and 546: A.3 MBIST and DFT interface A.3.1 M
Page 547 and 548: A.4 Preload engine interface Table
Page 549 and 550: A.6 Miscellaneous signals Table A-7
Page 551 and 552: Signal I/O Reset Description CFGNMF
Page 553 and 554: Signal I/O Reset Description DBGNOP
Page 555 and 556: Appendix B Instruction Mnemonics Th
Page 557 and 558: Instruction Mnemonics Table B-1 Adv
Page 559 and 560: Appendix C Revisions This appendix
Page 561 and 562: Revisions Added text to clarify des
Page 563 and 564: Glossary This glossary describes so
Page 565 and 566: Glossary Automatic Test Pattern Gen
Page 567 and 568: Big-endian memory Memory in which:
Page 569 and 570: Conditional execution Glossary incl
Page 571 and 572: Glossary Embedded Trace Macrocell (
Page 573 and 574: Illegal instruction An instruction
Page 575 and 576: Glossary NaN Not a number. A symbol
Page 577 and 578: Glossary Significand The component
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Glossary Watchpoint A watchpoint is
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