Cortex-A8 Technical Reference Manual - ARM Information Center

Table 3-34 shows the results of attempted access for each mode.
To access the Instruction Set Attributes Register 3, read CP15 with:
MRC p15, 0, , c0, c2, 3 ; Read Instruction Set Attributes Register 3
3.2.19 c0, Instruction Set Attributes Register 4
System Control Coprocessor
Table 3-34 Results of access to Instruction Set Attributes Register 3 a
Secure privileged Nonsecure privileged Secure User Nonsecure User
Read Write Read Write Read Write Read Write
Data Undefined Data Undefined Undefined Undefined Undefined Undefined
a. An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessor
instruction is executed.
The purpose of Instruction Set Attributes Register 4 is to provide information about the
instruction set that the processor supports beyond the basic set.
The Instruction Set Attributes Register 4 is:
• a read-only register common to the Secure and Nonsecure states
• accessible in privileged modes only.
Figure 3-15 shows the bit arrangement of the Instruction Set Attributes Register 4.
31 24 23 20 19 16 15 12 11 8 7 4 3 0
Reserved
Exclusive
instructions
Barrier
instructions
SMC
instructions
Write-back
instructions
With-shift Unprivileged
instructions instructions
Figure 3-15 Instruction Set Attributes Register 4 format
Table 3-35 shows how the bit values correspond with the Instruction Set Attributes Register 4
functions.
Bits Field Function
[31:24] - Reserved, RAZ.
Table 3-35 Instruction Set Attributes Register 4 bit functions
[23:20] Exclusive instructions Indicates support for exclusive instructions:
0x0 = The processor supports CLREX, LDREX{B|H}, and STREX{B|H}.
[19:16] Barrier instructions Indicates support for barrier instructions:
0x1 = The processor supports DMB, DSB, and ISB.
[15:12] SMC instructions Indicates support for SMC instructions:
0x1 = The processor supports SMC.
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