Cortex-A8 Technical Reference Manual - ARM Information Center

Table 3-137 shows the results of attempted access for each mode.
System Control Coprocessor
Table 3-137 Results of access to the Secure or Nonsecure Vector Base Address Register a
Secure privileged Nonsecure privileged Secure User Nonsecure User
Read Write Read Write Read Write Read Write
Secure
data
Secure
data
Nonsecure
data
To access the Secure or Nonsecure Vector Base Address Register, read or write CP15 with:
MRC p15, 0, , c12, c0, 0 ; Read Secure or Nonsecure Vector Base
; Address Register
MCR p15, 0, , c12, c0, 0 ; Write Secure or Nonsecure Vector Base
; Address Register
3.2.69 c12, Monitor Vector Base Address Register
Nonsecure
data
The purpose of the Monitor Vector Base Address Register is to hold the base address for the
Monitor mode exception vector. See Exceptions on page 2-27 for more information.
The Monitor Vector Base Address Register is:
• a read/write register in the Secure state only
• accessible in secure privileged modes only.
Figure 3-62 shows the bit arrangement of the Monitor Vector Base Address Register.
Figure 3-62 Monitor Vector Base Address Register format
Table 3-138 shows how the bit values correspond with the Monitor Vector Base Address
Register functions.
When an exception branches to the Monitor mode, the core branches to address:
Monitor_Base_Address + Exception_Vector_Address.
Undefined Undefined Undefined Undefined
a. An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessor
instruction is executed.
31 5 4 0
Bits Field Function
[31:5] Monitor vector
base address
[4:0] - Reserved. UNP, SBZ.
Monitor vector base address Reserved
Table 3-138 Monitor Vector Base Address Register bit functions
Holds the base address. Determines the location that the core branches to, on
a Monitor mode exception. The reset value is 0.
The Software Monitor Exception caused by an SMC instruction branches to Monitor mode. You
can configure IRQ, FIQ, and External abort exceptions to branch to Monitor mode, see c1,
Secure Configuration Register on page 3-53. These are the only exceptions that can branch to
Monitor mode and that use the Monitor Vector Base Address Register to calculate the branch
address. See Exceptions on page 2-27 for more information.
ARM DDI 0344K Copyright © 2006-2010 ARM Limited. All rights reserved. 3-118
ID060510 Non-Confidential