Cortex-A8 Technical Reference Manual - ARM Information Center

15.2 Trigger inputs and outputs
Trigger
Output
This section describes the trigger inputs and outputs that are available to the CTI.
Table 15-1 shows the trigger inputs available to the CTI.
Trigger input Name Clock domain Description
0 Debug entry a CLK Pulsed on entry to debug state
1 !nPMUIRQ CLK PMU generated interrupt
2 EXTOUT[0] CLK ETM external output
3 EXTOUT[1] CLK ETM external output
Table 15-2 shows the trigger outputs available to the CTI.
Cross Trigger Interface
Table 15-1 Trigger inputs
4 COMMRX CLK Debug communication receive channel is full
5 COMMTX CLK Debug communication transmit channel is empty
6 TRIGGER ATCLK ETM trigger
a. For revision r3 of the Cortex-A8 processor, this trigger is a pulse asserted on debug state entry. For revisions
r0 through r2, this trigger is a level-sensitive signal asserted while the processor is in debug state. This
level-sensitive signal is DBGTRIGGER.
Name Clock domain
Edge
detection
enable
Description
Table 15-2 Trigger outputs
0 EDBGRQ CLK - Causes the processor to enter debug state.
1 EXTIN[0] CLK ASICCTL[0] ETM external input.
2 EXTIN[1] CLK ASICCTL[1] ETM external input.
3 EXTIN[2] CLK ASICCTL[2] ETM external input.
4 EXTIN[3] CLK ASICCTL[3] ETM external input.
5 PMUEXTIN[0] CLK ASICCTL[4] PMU CTI event. This input can be selected by
the Event Selection Register. See c9, Event
Selection Register on page 3-84 for more
information on PMU events.
6 PMUEXTIN[1] CLK ASICCTL[5] PMU CTI event. This input can be selected by
the Event Selection Register. See c9, Event
Selection Register on page 3-84 for more
information on PMU events.
7 DBGRESTART CLK - Causes the processor to exit debug state.
8 !nCTIIRQ Asynchronous - Generates an interrupt if nCTIIRQ is connected
appropriately to the interrupt controller.
Note
• In revision r3 of the Cortex-A8 processor, trigger outputs 0 and 8 must be cleared by
software. See CTI Interrupt Acknowledge Register, CTIINTACK on page 15-11.
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