Cortex-A8 Technical Reference Manual - ARM Information Center

U
bit
PLE
bit
Table 3-128 shows the results of attempted access for each mode.
System Control Coprocessor
To access the PLE Control Register, set the PLE Channel Number Register to the appropriate
PLE channel and read or write CP15 with:
MRC p15, 0, , c11, c4, 0 ; Read PLE Control Register
MCR p15, 0, , c11, c4, 0 ; Write PLE Control Register
While the channel has the status of Running, any attempt to write to the PLE Control Register
results in architecturally Unpredictable behavior. For the processor, writes to the PLE Control
Register have no effect when the PLE channel is running.
3.2.64 c11, PLE Internal Start Address Register
The purpose of the PLE Internal Start Address Register for each channel is to define the start
address, that is, the first address that data transfers go to or from.
The PLE Internal Start Address Register is:
• a 32-bit read/write register with one register for each PLE channel common to Secure and
Nonsecure states
• accessible in User and privileged modes.
Table 3-128 Results of access to the PLE Control Registers a
Secure privileged Nonsecure privileged Secure User Nonsecure User
Read Write Read Write Read Write Read Write
0 0 Data Data Undefined Undefined Undefined Undefined Undefined Undefined
1 Data Data Data Data Undefined Undefined Undefined Undefined
1 0 Data Data Undefined Undefined Data Data Undefined Undefined
1 Data Data Data Data Data Data Data Data
a. An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessor
instruction is executed.
The PLE Internal Start Address Register bits [31:0] contain the Internal Start Virtual Address
(VA). Figure 3-57 shows this format.
31 5 4
0
virtual address UNP/SBZ
Figure 3-57 PLE Internal Start Address Register bit format
Access in the Nonsecure state depends on the PLE bit, see c1, Nonsecure Access Control
Register on page 3-56. The processor can access this register in User mode if the U bit for the
currently selected channel is set to 1, see c11, PLE User Accessibility Register on page 3-106.
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