Cortex-A8 Technical Reference Manual - ARM Information Center

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16.2.10 Branch instructions Instruction Cycle Timing Any write to the PC is considered a branch. This section describes both standard B branch instructions in addition to different instruction types with the PC as the destination register. In general, branch instructions schedule very well and have very few hazards that prevent superscalar issue. There are several properties to the execution of branches that make them behave differently than other instructions. Conditional branches Conditional branches are executed differently than other conditional instructions. Most conditional instructions take the destination register as an additional source and the condition codes are resolved in E2. Branches do not require the destination register, PC, as an additional source because they already use the PC as a source. They are also different than normal conditional operations because the flags resolve the condition codes in E3 rather than E2. This enables the pairing of a flag setting instruction and a branch in the same cycle. Branches with the PC as a source or destination Using the PC as a source register does not generally result in scheduling hazards as for the case of a general-purpose register. This is because the PC values are predicted in the pipeline and are readily available to each instruction without any forwarding required. The only exception to this rule is that an instruction with a PC as a source register cannot be dual issued with an instruction that uses the PC as a destination register. Other than the dual issue restriction, using the PC as a destination register does not result in a hazard for subsequent instructions for the same reason. Data processing-based branches Data processing branches can have the same data hazards of nonbranch versions of these instructions for operands other than the PC. Load-based branches An LDR PC or LDM PC instruction behaves like a normal load with the exception that it requires one additional cycle to execute. Table 16-11 shows the behavior of branch instructions. Table 16-11 Branch instructions Shift type Cycles Source1 Source2 Source3 Source4 Result1 Result2 BCC 1 [Flags:E3] - - - R15:E4 a - BLCC, BLX 1 [Flags:E3] - - - R14:E3 R15:E4 a BXCC 1 [Flags:E3] Rm:E2 - - - - Data-processing branch b Typically 1 c [Flags:E3] - - - R15:E4 a - Load-based branch Basic load plus one cycle d [Flags:E3] - - - (Rn:E2) - a. Branch prediction resolution in E4. b. ADD PC, R1, R2 and MOV PC, R4 are both examples of data-processing branches. c. See Data-processing instructions on page 16-4 for more information on cycle counts and source registers. ARM DDI 0344K Copyright © 2006-2010 ARM Limited. All rights reserved. 16-9 ID060510 Non-Confidential
d. See Load/store instructions on page 16-7 for more information on cycle counts and source registers. 16.2.11 Coprocessor instructions Instruction Cycle Timing The CP15 and CP14 instructions are used to access special-purpose registers that are distributed across the design. They also perform very specialized operations such as cache maintenance. The instructions affected are listed in Table 16-12 and in Table 16-13. The minimum time to complete these CP15 and CP14 operations is 60 cycles. However, the timing of these instructions varies highly. It can take hundreds of cycles, depending on the operation and on the current processor activity. Instruction Op1 CRn CRm Op2 Function Table 16-12 Nonpipelined CP14 instructions Instruction Op1 CRn CRm Op2 MCR/MRC p14 0 Rd c0-c15 c0-c15 0-7 MCR p15 0 Rd c1 c0 0 Control Register Table 16-13 Nonpipelined CP15 instructions MCR p15 0 Rd c1 c0 1 Auxiliary Control Register MCR p15 0 Rd c2 c0 0 Translation Table Base 0 Register MCR p15 0 Rd c2 c0 1 Translation Table Base 1 Register MCR p15 0 Rd c2 c0 2 Translation Table Base Control Register MCR p15 0 Rd c3 c0 0 Domain Access Control Register MCR/MRC p15 0 Rd c5 c0 0 Data Fault Status Register MCR/MRC p15 0 Rd c5 c0 1 Instruction Fault Status Register MCR/MRC p15 0 Rd c5 c1 0 Data Auxiliary Fault Status Register MCR/MRC p15 0 Rd c5 c1 1 Instruction Auxiliary Fault Status Register MCR/MRC p15 0 Rd c6 c0 0 Data Fault Address Register MCR/MRC p15 0 Rd c6 c0 1 Instruction Fault Address Register MCR p15 0 Rd c7 c5 1 Invalidate I$ Line by MVA to PoU MCR p15 0 Rd c7 c6 1 Invalidate D$ Line by MVA to PoC MCR p15 0 Rd c7 c6 2 Invalidate D$ Line by Set/Way MCR p15 0 Rd c7 c8 0-3 VA-to-PA translation in the Current World MCR p15 0 Rd c7 c8 4-7 VA-to-PA translation in the Other World MCR p15 0 Rd c7 c10 1 Clean D$ Line by MVA to PoC MCR p15 0 Rd c7 c10 2 Clean D$ Line by Set/Way MCR p15 0 Rd c7 c10 4 Data Synchronization Barrier MCR p15 0 Rd c7 c10 5 Data Memory Barrier ARM DDI 0344K Copyright © 2006-2010 ARM Limited. All rights reserved. 16-10 ID060510 Non-Confidential
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Copyright © 2006-2010 ARM Limited.
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Web Address http://www.arm.com ARM
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Contents 2.14 The program status re
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Contents 16.6 Instruction-specific
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List of Tables Table 3-16 Debug Fea
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List of Tables Table 3-136 Secure o
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List of Tables Table 12-59 Values t
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List of Figures Cortex-A8 Technical
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List of Figures Figure 3-77 BTB arr
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List of Figures Figure 15-16 CTI Ch
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About this manual Product revision
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old Highlights interface elements,
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Feedback Feedback on the product Fe
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1.1 About the processor Introductio
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1.3 Components of the processor L1
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1.3.6 NEON 1.3.7 ETM The NEON unit
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1.5 Debug Introduction The processo
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1.7 Configurable options Table 1-1
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Introduction • The various data a
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1.9.6 r2p0-r2p1 1.9.7 r2p1-r2p2 1.9
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Chapter 2 Programmers Model This ch
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2.2 Thumb-2 instruction set Program
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Bits Field Function Programmers Mod
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2.4 Jazelle Extension 2.4.1 Jazelle
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2.5 Security Extensions architectur
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2.6 Advanced SIMD architecture Prog
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2.8 Processor operating states 2.8.
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2.10 Memory formats 2.10.1 Byte-inv
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2.12 Operating modes Programmers Mo
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System and User r0 r1 r2 r3 r4 r5 r
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2.14 The program status registers 2
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2.14.5 The GE[3:0] bits Programmers
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Mode bits Programmers Model M[4:0]
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2.15 Exceptions 2.15.1 Exception en
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2.15.5 Interrupt request 2.15.6 Abo
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This restores both the PC and the C
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2.15.13 Exception priorities Progra
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2.17 Hardware consideration for Sec
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SECMONOUT[78] instruction caches at
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Chapter 3 System Control Coprocesso
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System Control Coprocessor Register
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3.1.3 MMU control and configuration
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3.2 System control coprocessor regi
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CRn Op1 CRm Op2 Register or operati
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3.2.2 c0, Main ID Register System C
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3.2.4 c0, TCM Type Register 3.2.5 c
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3.2.7 c0, Processor Feature Registe
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• accessible in privileged modes
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System Control Coprocessor Table 3-
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Bits Field Function [11:8] L1 Harva
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Bits Field Function [11:8] Harvard
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31 28 27 24 23 20 19 16 15 12 11 8
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Table 3-30 shows the results of att
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System Control Coprocessor 31 28 27
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Table 3-36 shows the results of att
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• accessible in privileged modes
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CSSR Size 3.2.24 c0, Cache Size Sel
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System Control Coprocessor 31 30 29
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MCR p15, 0, , c1, c0, 0 ; Write Con
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Bits Field [19] Clock stop request
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Bits Field Security State NS S Tabl
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3.2.28 c1, Secure Configuration Reg
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AW EA Function Table 3-55 shows the
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3.2.32 c2, Translation Table Base R
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System Control Coprocessor Figure 3
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Bits Field Function 3.2.35 c5, Data
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3.2.36 c5, Instruction Fault Status
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3.2.38 c6, Data Fault Address Regis
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System Control Coprocessor Note •
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System Control Coprocessor Figure 3
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3.2.41 c8, TLB operations The data
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Figure 3-38 shows the bit arrangeme
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EN b 3.2.44 c9, Count Enable Clear
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EN b 3.2.46 c9, Software Increment
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EN b 3.2.48 c9, Cycle Count Registe
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EN b Table 3-96 shows the results o
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Value Description 0x44 Any cacheabl
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DBGEN || NIDEN 3.2.51 c9, User Enab
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EN 3.2.53 c9, Interrupt Enable Clea
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Figure 3-48 shows the bit arrangeme
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3.2.55 c9, L2 Cache Auxiliary Contr
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Bits Field Function [8:6] Tag RAM l
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TL bit value 3.2.57 c10, TLB preloa
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The PLE Identification and Status R
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3.2.62 c11, PLE enable commands U b
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Bits Field Function System Control
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U bit PLE bit Table 3-129 shows the
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U bit PLE bit System Control Coproc
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3.2.68 c12, Secure or Nonsecure Vec
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3.2.70 c12, Interrupt Status Regist
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The FCSE PID Register is: • a rea
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TLB CAM read/write TLB ATTR read/wr
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MCR p15 0, , c15, c3, 4 ; I-L1 TLB
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31 27 26 22 21 0 Reserved L1 Data 0
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System Control Coprocessor The L1 H
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3.2.78 c15, L1 data array operation
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Instruction L1 Data 0 register Inst
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Parity/ECC RAM read/write Data RAM
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3.2.82 c15, L2 parity/ECC array ope
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3.2.84 c15, L2 data array operation
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4.1 About unaligned and mixed-endia
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Unaligned Data and Mixed-endian Dat
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Chapter 5 Program Flow Prediction T
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5.2 Predicted instructions Program
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Program Flow Prediction Because ret
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5.4 Guidelines for optimal performa
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5.6 Operating system and predictor
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6.1 About the MMU Memory Management
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6.3 16MB supersection support Memor
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6.5 External aborts 6.5.1 External
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6.7 MMU software-accessible registe
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7.1 About the L1 memory system Leve
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7.2.6 Instruction cache maintenance
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L1 inner policy a L2 outer policy N
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7.5 Data cache features 7.5.1 Data
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7.7 Hardware support for virtual al
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Chapter 8 Level 2 Memory System Thi
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8.2 Cache organization 8.2.1 L2 cac
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8.3 Enabling and disabling the L2 c
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Level 2 Memory System Note It is en
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Level 2 Memory System Note You must
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Lock address : LockAddr Lock free :
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8.7 Parity and error correction cod
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9.1 About the external memory inter
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Integer data and CP14 writes Noncac
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9.4 AXI data read/write transaction
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Noncacheable, or strongly ordered,
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Noncacheable store word Noncacheabl
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LA Last Access External Memory Inte
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10.1 Clock domains 10.1.1 AXI clock
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10.2 Reset domains 10.2.1 Power-on
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REFCLK (PLL input) nPORESET ARESETn
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10.3 Power control 10.3.1 Dynamic p
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Clock, Reset, and Power Control the
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ATB APB I/O clamp I/O clamp L/S = L
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ATB APB I/O clamp I/O clamp LS = Le
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Clock, Reset, and Power Control 3.
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Powering up the debug and ETM domai
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7. Perform a normal software reset
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Clock, Reset, and Power Control 5.
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Chapter 11 Design for Test This cha
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In L1 MBIST Instruction Register Fi
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Note Do not test the CAMBIST arrays
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• number of rows of the L2 data,
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Design for Test Not all row setting
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In Design for Test Figure 11-4 show
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Design for Test When testing the ta
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CLK ARESETn MBISTMODE MBISTSHIFT MB
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End-of-test datalog retrieval Desig
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Pattern N RWRXMARCH 8N Row-fast Sta
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4. rscan array, data_seed = invert.
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3. R_, W, R, decr. 4. rscan data fr
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• the data after pass 1 of XADDRB
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(1 + (2 17)) 2 17 = 4,587,520 cycle
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processor input ports WEXTEST WINTE
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Design for Test toggling during shi
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12.1 Debug systems 12.1.1 Debug hos
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12.2.3 Security extensions and debu
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Instruction Mnemonic Description 12
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12.3.6 Power domains and debug 12.3
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Table 12-5 shows the APB interface
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12.4 Debug register descriptions Te
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MRC p14, 0, , c0, c0, 0 ; Read Debu
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31 30 29 28 27 26 25 24 23 22 21 20
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Bits Field Function [21:20] DTR acc
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Bits Field Function To access the D
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12.4.7 Watchpoint Fault Address Reg
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Bits Access Normal address [2] RW V
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12.4.12 Debug Run Control Register
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Table 12-23 shows how the bit value
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BVR[22:20] Meaning b011 The corresp
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Bits Field Function [15:14] Secure
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12.4.18 Operating System Lock Statu
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Debug • The sequence can be aband
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12.5 Management registers Offset Th
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Offset Register number Mnemonic Fun
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Bits Field Function [5] nDMAIRQ nDM
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12.5.7 Claim Tag Clear Register 12.
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12.5.10 Authentication Status Regis
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Table 12-45 shows fields that are i
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12.6 Debug events 12.6.1 Software d
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12.6.5 Watchpoint debug events If a
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Table 12-53 shows the values in the
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12.8 Debug state 12.8.1 Entering de
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12.8.4 Writing to the CPSR in debug
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Mode SCR[0] For CP15 instructions,
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12.8.9 Leaving debug state Imprecis
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12.9.3 Cache usage profiling Debug
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Note DBGPWRDWNREQ must be tied LOW
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If software running on the processo
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Rules for accessing the DCC At the
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} While the processor is running, i
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Debug Table 12-59 Values to write t
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12.11.4 Debug state entry Example 1
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} // Step 1. Update the CPSR value
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Writing the CPSR in debug state Exa
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Debug Example 12-21 Reading a word
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} // Step 9. Check for aborts. abor
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12.12 Debugging systems with energy
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MOV r0, r4 POP {r4, pc} Example 12-
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Chapter 13 NEON and VFP Programmers
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13.2 General-purpose registers 13.2
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13.3 Short vectors 13.3.1 About reg
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13.3.2 Operations using register ba
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NEON and VFP Programmers Model The
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Note All hardware ID information is
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Bits Field Function [12:8] - Reserv
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NEON and VFP Programmers Model Tabl
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13.6 Compliance with the IEEE 754 s
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Underflow NEON and VFP Programmers
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14.1 About the ETM 14.1.1 ETM featu
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14.1.3 NEON Bridge and bus matrix A
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14.3 ETM register summary The ETM r
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Bits Field Function [11:8] Major ET
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Page 453 and 454: Embedded Trace Macrocell Table 14-1
Page 457 and 458: 14.5.3 Enabling events 14.5.4 Addre
Page 459 and 460: 14.7 Context ID tracing Embedded Tr
Page 461 and 462: 14.9 Idle state control Embedded Tr
Page 465 and 466: Chapter 15 Cross Trigger Interface
Page 467 and 468: CTICHIN[0] CTICHIN[1] CTICHIN[2] CT
Page 469 and 470: 15.2 Trigger inputs and outputs Tri
Page 471 and 472: 15.3 Connecting asynchronous channe
Page 473 and 474: 15.5 CTI register summary Address o
Page 475 and 476: 15.6 CTI register descriptions This
Page 477 and 478: 15.6.4 CTI Application Trigger Clea
Page 479 and 480: Table 15-10 shows how the bit value
Page 481 and 482: 15.6.12 ASIC Control Register, ASIC
Page 483 and 484: 15.7 CTI Integration Test Registers
Page 485 and 486: 15.7.4 ITTRIGOUTACK, 0xEF0 15.7.5 I
Page 487 and 488: Cross Trigger Interface Table 15-26
Page 489 and 490: 15.8.3 Device Type Identifier, 0xFC
Page 491 and 492: Cross Trigger Interface Table 15-31
Page 493 and 494: 16.1 About instruction cycle timing
Page 495 and 496: Instruction Cycle Timing Example 16
Page 497 and 498: Table 16-4 shows the operation of m
Page 499: Table 16-9 shows the operation of l
Page 503 and 504: Instruction Cycle Timing Table 16-1
Page 505 and 506: 16.4 Other pipeline-dependent laten
Page 507 and 508: 16.4.5 Conditional instructions Ins
Page 509 and 510: 16.6 Instruction-specific schedulin
Page 511 and 512: Instruction Cycle Timing VNEG Dd,Dm
Page 513 and 514: VMLA a VMLS a VMLAa VMLSa VQDMLAa V
Page 515 and 516: VSLI VSRI 16.6.5 Advanced SIMD floa
Page 517 and 518: 16.6.6 Advanced SIMD byte permute i
Page 519 and 520: Instruction Table 16-23 shows the o
Page 521 and 522: Instruction VST3 3-reg (unaligned)
Page 523 and 524: Instruction VLD3 3-reg (unaligned)
Page 525 and 526: Instruction Single precision cycles
Page 527 and 528: • FMACS, FNMACS • FMSCS, FNMSCS
Page 529 and 530: is dual issued with previous instru
Page 531 and 532: 17.1 About setup and hold times AC
Page 533 and 534: 17.2 AXI interface Table 17-2 shows
Page 535 and 536: 17.3 ATB and CTI interfaces Table 1
Page 537 and 538: AC Characteristics Table 17-4 Timin
Page 539 and 540: 17.6 L2 preload interface AC Charac
Page 541 and 542: 17.8 Miscellaneous signals AC Chara
Page 543 and 544: A.1 AXI interface Signal Descriptio
Page 545 and 546: A.3 MBIST and DFT interface A.3.1 M
Page 547 and 548: A.4 Preload engine interface Table
Page 549 and 550: A.6 Miscellaneous signals Table A-7
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Signal I/O Reset Description CFGNMF
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Signal I/O Reset Description DBGNOP
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Appendix B Instruction Mnemonics Th
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Instruction Mnemonics Table B-1 Adv
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Appendix C Revisions This appendix
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Revisions Added text to clarify des
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Glossary This glossary describes so
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Glossary Automatic Test Pattern Gen
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Big-endian memory Memory in which:
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Conditional execution Glossary incl
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Glossary Embedded Trace Macrocell (
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Illegal instruction An instruction
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Glossary NaN Not a number. A symbol
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Glossary Significand The component
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Glossary Watchpoint A watchpoint is
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