Cortex-A8 Technical Reference Manual - ARM Information Center

Signal I/O Reset Description
SECMONOUT[86:0] O Undefined Security monitor output:
[19:0] = pipeline 0 instruction address bits[31:12]
[39:20] = pipeline 1 instruction address bits[31:12]
[59:40] = L1 data address bits[31:12]
[64:60] = exception encoding
[69:65] = CPSR[4:0] = mode bits, M[4:0]
[73:70] = CPSR[8:5] = bits A, I, F, and T
[74] = CPSR[24] = J bit
[75] = CP15 Secure Configuration Register bit[0], NS
[76] = CP15 Secure Control Register bit[0], M
[77] = CP15 Secure Control Register bit[2], C
[78] = CP15 Secure Control Register bit[12], I
[79] = IMB instruction executed flag
[80] = DMB or DWB instruction executed flag
[81] = pipeline 0 instruction address valid flag
[82] = pipeline 1 instruction address valid flag
[83] = condition code fail pipeline 0 valid flag
[84] = condition code fail pipeline 1 valid flag
[85] = exception valid flag
[86] = L1 data address valid flag.
STANDBYWFI O b0 Standby mode flag generated by WFI operation:
0 = processor not in standby mode
1 = processor in standby mode.
Signal Descriptions
Table A-7 Miscellaneous signals (continued)
nFIQ I - Active-LOW asynchronous fast interrupt request:
0 = activate fast interrupt
1 = do not activate fast interrupt.
The processor treats the nFIQ input as level sensitive. The nFIQ
input must be asserted until the processor acknowledges the interrupt.
nIRQ I - Active-LOW asynchronous interrupt request:
0 = activate interrupt
1 = do not activate interrupt.
The processor treats the nIRQ input as level sensitive. The nIRQ
input must be asserted until the processor acknowledges the interrupt.
VINITHI I - Controls the location of the exception vectors at reset:
0 = starts exception vectors at address 0x00000000
1 = starts exception vectors at address 0xFFFF0000.
This pin is only sampled during reset of the processor.
CFGTE I - Controls the state of TE bit in the CP15 c1 Control Register at reset:
0 = TE bit is LOW
1 = TE bit is HIGH.
This pin is only sampled during reset of the processor.
CFGEND0 I - Controls the state of EE bit in the CP15 c1 Control Register at reset:
0 = EE bit is LOW
1 = EE bit is HIGH.
This pin is only sampled during reset of the processor.
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