Cortex-A8 Technical Reference Manual - ARM Information Center

13.6 Compliance with the IEEE 754 standard
NEON and VFP Programmers Model
The VFP coprocessor is fully compliant with the IEEE 754 standard in hardware, no support
code is required to achieve this compliance.
See the ARM Architecture Reference Manual for information about VFP architectural
compliance with the IEEE 754 standard.
13.6.1 Complete implementation of the IEEE 754 standard
The following operations from the IEEE 754 standard are not supplied by the VFP instruction
set:
• remainder
• round floating-point number to integer-valued floating-point number
• binary-to-decimal conversions
• decimal-to-binary conversions
• direct comparison of single-precision and double-precision values.
For complete implementation of the IEEE 754 standard, the VFP coprocessor must be
augmented with library functions that implement these operations. See Application Note 98,
VFP Support Code for details of the available library functions.
13.6.2 IEEE 754 standard implementation choices
Some of the implementation choices permitted by the IEEE 754 standard and used in the VFPv3
architecture are described in the ARM Architecture Reference Manual.
NaN handling
Any single-precision or double-precision values with the maximum exponent field value and a
nonzero fraction field are valid NaNs. A most significant fraction bit of zero indicates a
Signaling NaN (SNaN). A one indicates a Quiet NaN (QNaN). Two NaN values are treated as
different NaNs if they differ in any bit. Table 13-13 shows the default NaN values in both single
and double precision.
Table 13-13 Default NaN values
Single-precision Double-precision
Sign 0 0
Exponent 0xFF 0x7FF
Fraction bit [22] = 1 bits [21:0] are all zeros bit [51] = 1 bits [50:0] are all zeros
Any SNaN passed as input to an operation causes an Invalid Operation exception and sets the
IOC flag, FPSCR[0], to 1. A default QNaN is written to the destination register. The rules for
cases involving multiple NaN operands are in the ARM Architecture Reference Manual.
Processing of input NaNs for ARM floating-point coprocessors and libraries is defined as
follows:
• In full-compliance mode, NaNs are handled according to the ARM Architecture Reference
Manual. The hardware processes the NaNs directly for arithmetic CDP instructions. For
data transfer operations, NaNs are transferred without raising the Invalid Operation
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