Cortex-A8 Technical Reference Manual - ARM Information Center

CLK
ARESETn
MBISTMODE
MBISTSHIFT
MBISTDSHIFT
MBISTDATAIN
MBISTRUN
MBISTRESULT[2:0]
Bitmap test mode
Design for Test
In bitmap test mode, the MBIST controller stops when it detects a failure. It asserts
MBISTRESULT[1] until the tester begins datalog retrieval. After datalog retrieval, the MBIST
controller resumes the test from the point where it stopped. This handshake continues until test
completion. The collected datalogs are useful for offline bitmap and redundancy analysis.
In bitmap test mode, an MBIST test consists of the following steps:
1. MBIST pipeline flush. Assert the system reset signal for at least 15 cycles.
2. Instruction load. Write to the MBIST Instruction Register.
3. Test execute.
a. If failures are detected, go to step 4.
b. If no failure is detected, go to step 5.
4. Datalog retrieval. Go to step 3 to continue.
5. End of test.
MBIST Instruction load
Figure 11-7 shows the timing of an MBIST instruction load. The MBISTMODE signal must
remain asserted while the core is under reset. See Figure 10-5 on page 10-5 for more
information on reset timing. MBISTSHIFT is asserted and instruction load data is serially
loaded into the Instruction Register through the MBISTDATAIN pin. MBISTSHIFT is
deasserted on completion of the instruction load. MBISTDATAIN has one cycle of latency in
relation to MBISTSHIFT.
Instr[lsb] Instr[lsb+1] Instr [msb-1] Instr [msb]
One-cycle MBISTDATAIN latency after MBISTSHIFT
MBIST custom GO-NOGO instruction load
Figure 11-7 Timing of MBIST instruction load
Figure 11-8 on page 11-16 shows an example of an MBIST instruction load followed
immediately by a GO-NOGO instruction load. During the GO-NOGO portion of the load,
MBISTDSHIFT and MBISTSHIFT both equal 1.
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