Cortex-A8 Technical Reference Manual - ARM Information Center

9.1 About the external memory interface
External Memory Interface
The external memory interface enables the processor to interface with third level caches,
peripherals, and external memory. You can configure the processor to connect to either a 64-bit
or 128-bit AXI interconnect that provides flexibility to system designs. The external memory
interface supports the following interfaces:
• read address channel
• read data/response channel
• write address channel
• write data channel
• write response channel.
All internal requests that require access to an external interface must use the appropriate external
interface. You can generate requests with the following:
• instruction fetch unit
• load/store unit
• table walk
• preload engine
• internal L2 cache controller.
By using the features of the AXI interconnect that enable split address and data transactions, in
addition to multiple outstanding requests, the processor can reduce the external pin interface
without reducing performance. The processor has a single AXI master interface. It does not
contain an AXI slave interface.
9.1.1 External interface servicing instruction fetch transactions
The L2 memory system handles all instruction-side cache misses, including those for
noncacheable memory. All instruction fetch requests are read-only and are routed to the external
read address and data channels. For cacheable memory accesses, a wrapping burst transaction
is generated to fetch an entire cache line from external memory. A nonwrapping burst
transaction is generated by the L2 memory system for noncacheable, strongly ordered, or device
memory instruction fetch accesses. See Table 9-5 on page 9-5 for information on AXI
instruction transactions.
9.1.2 External interface servicing data transactions
The L2 memory system handles all data-side cache misses, including those for noncacheable
memory, and those generated by the preload engine. Read data accesses are routed to the read
address and data channels, whereas write data accesses are routed to the write address and data
channels. Swap and semaphore instruction support is also built into the L2 memory system and
external interface that are unique to data-side accesses.
Cacheable accesses generate a wrapping burst transaction on the external interface. Strongly
ordered, device, and noncacheable accesses typically result in single transaction requests to
external interface. See Table 9-7 on page 9-7 for information on data transactions.
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