Cortex-A8 Technical Reference Manual - ARM Information Center

Parity/ECC RAM
read/write
Data RAM read/
write
Tag RAM read/write
Data RAM read/write
Data RAM read/write
System Control Coprocessor
31 16 15 13 12 8 7 5 4 2 1 0
Figure 3-81 L2 Data 0 Register format
Figure 3-82 shows the bit arrangement of the L2 Data 1 Register when retrieving or registering
data as a result of the read/write operations.
Figure 3-82 L2 Data 1 Register format
Figure 3-83 shows the bit arrangement of the L2 Data 2 Register when retrieving or registering
data as a result of the read/write operations.
31
31
Reserved
Data
Figure 3-83 L2 Data 2 Register format
Table 3-158 shows how the bit values correspond with the L2 Data 0 Register functions as a
result of an L2 parity/ECC read/write operation.
To perform an L2 parity/ECC operation, read or write CP15 with:
MCR p15, 0, c15, c8, 4 ; L2 parity and ECC write
MCR p15, 0, c15, c9, 4 ; L2 parity and ECC read
Reserved
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Data
Data
Reserved
Data
Data Data
Reserved
Table 3-158 Functional bits of L2 Data 0 Register for an L2 parity/ECC operation
Bits Field Function
[31:16] - Reserved. UNP, SBZ.
Data
[15:0] Data Holds L2 parity/ECC information.
1
0
0