Cortex-A8 Technical Reference Manual - ARM Information Center

9.2 AXI control signals in the processor
9.2.1 AXI identifiers
For additional information about AXI control signals, see the AMBA AXI Protocol
Specification.
External Memory Interface
The AXI interconnect uses identifiers with each transaction that enables requests to be serviced
out-of-order under certain circumstances. The processor supports multiple outstanding
transactions and assigns unique IDs to each specific transaction. There are two sets of
identifiers, one for the read address channel, ARRID[3:0], and one for the write address
channel, AWRID[3:0]. Table 9-1 shows the AXI ID assignment for read address channel.
Table 9-2 shows the AXI ID assignment for write address channel.
Table 9-1 Read address channel AXI ID
Read address channel request type ID tag value
Instruction fetch L2 cacheable b1000-b1011
L1 cacheable (L2 non-cacheable) b1111
Noncacheable or Strongly Ordered b0100
Shared or nonshared device b0101
Integer data and CP14 loads L2 cacheable b1000-b1011
L1 cacheable (L2 non-cacheable) b1110
Noncacheable or Strongly Ordered b0000
Shared device b0001
Nonshared device b0011
NEON and VFP loads L2 cacheable b1000-b1011
Noncacheable or Strongly Ordered b0000
Shared device b0001
Nonshared device b0011
Table Walks L2 cacheable b1000-b1011
Noncacheable b0110
PLD and PLE L2 cacheable b1000-b1011
Table 9-2 Write address channel AXI ID
Write address channel request type ID tag value
Evictions from L2 cache Each ID corresponds to one eviction in the L2 cache b1000 - b1011
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