Cortex-A8 Technical Reference Manual - ARM Information Center

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A.3.2 DFT pins and additional MBIST pin requirements during MBIST testing Signal I/O Signal Descriptions Table A-4 shows the signals necessary for DFT. It also shows the additional pins required during MBIST testing. Value during functional mode Table A-4 DFT and additional MBIST pin requirements Value during MBIST mode Description MBISTMODEL1 I 0 1 Configures L1 for MBIST mode and disables instruction fetch after reset. MBISTMODEL2 I 0 1 Configures L2 for MBIST mode and disables instruction fetch after reset. TESTMODE I 0 0 Indicates ATPG test mode. Deassert during MBIST mode. TESTCGATE I 0 1 Controls core clock gating during test mode or MBIST mode. TESTEGATE I 0 0 Controls ETM clock gating. Deassert to save power during MBIST mode. TESTNGATE I 0 0 Controls NEON clock gating. Deassert to save power during MBIST mode. SE I 0 0 Scan enable signal. Ensures safe shifting of scan chains. SAFESHIFTRAMIF I 0 0 Prevents the RAM in the instruction fetch unit from performing a write operation during scan shifting. SAFESHIFTRAMLS I 0 0 Prevents the RAM in the load/store unit from performing a write operation during scan shifting. SAFESHIFTRAML2 I 0 0 Prevents the RAM in the L2 cache unit from performing a write operation during scan shifting. SERIALTEST I 0 0 Concatenates the wrapper boundary register scan cells into a single scan chain. SHIFTWR I 0 0 IEEE 1500 standard shift signal. CAPTUREWR I 0 0 IEEE 1500 standard capture signal. WINTEST I 0 0 Enables internal testing during ATPG. WEXTEST I 0 0 Enables external testing during ATPG. WSE I 0 0 Wrapper scan enable. Enables serial shifting of the wrapper scan chain. PRESETn I - 0 Active-LOW APB reset input. ACLKEN I - 1 AXI clock enable signal. This signal must be driven HIGH for at least one clock cycle during reset. The value after reset does not affect the MBIST operation. ARM DDI 0344K Copyright © 2006-2010 ARM Limited. All rights reserved. A-5 ID060510 Non-Confidential
A.4 Preload engine interface Table A-5 shows the L2 preload signals. Signal I/O Reset Description Signal Descriptions Table A-5 Preload engine interface nDMAEXTERRIRQ O b1 Active-LOW interrupt on error for all transfers: 0 = interrupt active 1 = interrupt not active. nDMAIRQ O b1 Active-LOW interrupt on completion for nonsecure transfers: 0 = interrupt active 1 = interrupt not active. nDMASIRQ O b1 Active-LOW interrupt on completion for secure transfers: 0 = interrupt active 1 = interrupt not active. ARM DDI 0344K Copyright © 2006-2010 ARM Limited. All rights reserved. A-6 ID060510 Non-Confidential
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Copyright © 2006-2010 ARM Limited.
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Web Address http://www.arm.com ARM
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Contents 2.14 The program status re
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Contents 16.6 Instruction-specific
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List of Tables Table 3-16 Debug Fea
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List of Tables Table 3-136 Secure o
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List of Tables Table 12-59 Values t
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List of Figures Cortex-A8 Technical
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List of Figures Figure 3-77 BTB arr
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List of Figures Figure 15-16 CTI Ch
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About this manual Product revision
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old Highlights interface elements,
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Feedback Feedback on the product Fe
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1.1 About the processor Introductio
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1.3 Components of the processor L1
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1.3.6 NEON 1.3.7 ETM The NEON unit
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1.5 Debug Introduction The processo
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1.7 Configurable options Table 1-1
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Introduction • The various data a
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1.9.6 r2p0-r2p1 1.9.7 r2p1-r2p2 1.9
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Chapter 2 Programmers Model This ch
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2.2 Thumb-2 instruction set Program
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Bits Field Function Programmers Mod
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2.4 Jazelle Extension 2.4.1 Jazelle
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2.5 Security Extensions architectur
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2.6 Advanced SIMD architecture Prog
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2.8 Processor operating states 2.8.
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2.10 Memory formats 2.10.1 Byte-inv
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2.12 Operating modes Programmers Mo
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System and User r0 r1 r2 r3 r4 r5 r
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2.14 The program status registers 2
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2.14.5 The GE[3:0] bits Programmers
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Mode bits Programmers Model M[4:0]
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2.15 Exceptions 2.15.1 Exception en
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2.15.5 Interrupt request 2.15.6 Abo
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This restores both the PC and the C
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2.15.13 Exception priorities Progra
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2.17 Hardware consideration for Sec
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SECMONOUT[78] instruction caches at
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Chapter 3 System Control Coprocesso
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System Control Coprocessor Register
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3.1.3 MMU control and configuration
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3.2 System control coprocessor regi
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CRn Op1 CRm Op2 Register or operati
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3.2.2 c0, Main ID Register System C
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3.2.4 c0, TCM Type Register 3.2.5 c
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3.2.7 c0, Processor Feature Registe
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• accessible in privileged modes
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System Control Coprocessor Table 3-
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Bits Field Function [11:8] L1 Harva
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Bits Field Function [11:8] Harvard
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31 28 27 24 23 20 19 16 15 12 11 8
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Table 3-30 shows the results of att
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System Control Coprocessor 31 28 27
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Table 3-36 shows the results of att
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• accessible in privileged modes
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CSSR Size 3.2.24 c0, Cache Size Sel
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System Control Coprocessor 31 30 29
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MCR p15, 0, , c1, c0, 0 ; Write Con
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Bits Field [19] Clock stop request
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Bits Field Security State NS S Tabl
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3.2.28 c1, Secure Configuration Reg
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AW EA Function Table 3-55 shows the
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3.2.32 c2, Translation Table Base R
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System Control Coprocessor Figure 3
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Bits Field Function 3.2.35 c5, Data
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3.2.36 c5, Instruction Fault Status
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3.2.38 c6, Data Fault Address Regis
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System Control Coprocessor Note •
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System Control Coprocessor Figure 3
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3.2.41 c8, TLB operations The data
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Figure 3-38 shows the bit arrangeme
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EN b 3.2.44 c9, Count Enable Clear
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EN b 3.2.46 c9, Software Increment
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EN b 3.2.48 c9, Cycle Count Registe
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EN b Table 3-96 shows the results o
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Value Description 0x44 Any cacheabl
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DBGEN || NIDEN 3.2.51 c9, User Enab
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EN 3.2.53 c9, Interrupt Enable Clea
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Figure 3-48 shows the bit arrangeme
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3.2.55 c9, L2 Cache Auxiliary Contr
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Bits Field Function [8:6] Tag RAM l
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TL bit value 3.2.57 c10, TLB preloa
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The PLE Identification and Status R
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3.2.62 c11, PLE enable commands U b
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Bits Field Function System Control
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U bit PLE bit Table 3-129 shows the
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U bit PLE bit System Control Coproc
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3.2.68 c12, Secure or Nonsecure Vec
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3.2.70 c12, Interrupt Status Regist
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The FCSE PID Register is: • a rea
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TLB CAM read/write TLB ATTR read/wr
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MCR p15 0, , c15, c3, 4 ; I-L1 TLB
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31 27 26 22 21 0 Reserved L1 Data 0
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System Control Coprocessor The L1 H
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3.2.78 c15, L1 data array operation
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Instruction L1 Data 0 register Inst
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Parity/ECC RAM read/write Data RAM
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3.2.82 c15, L2 parity/ECC array ope
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3.2.84 c15, L2 data array operation
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4.1 About unaligned and mixed-endia
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Unaligned Data and Mixed-endian Dat
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Chapter 5 Program Flow Prediction T
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5.2 Predicted instructions Program
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Program Flow Prediction Because ret
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5.4 Guidelines for optimal performa
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5.6 Operating system and predictor
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6.1 About the MMU Memory Management
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6.3 16MB supersection support Memor
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6.5 External aborts 6.5.1 External
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6.7 MMU software-accessible registe
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7.1 About the L1 memory system Leve
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7.2.6 Instruction cache maintenance
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L1 inner policy a L2 outer policy N
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7.5 Data cache features 7.5.1 Data
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7.7 Hardware support for virtual al
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Chapter 8 Level 2 Memory System Thi
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8.2 Cache organization 8.2.1 L2 cac
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8.3 Enabling and disabling the L2 c
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Level 2 Memory System Note It is en
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Level 2 Memory System Note You must
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Lock address : LockAddr Lock free :
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8.7 Parity and error correction cod
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9.1 About the external memory inter
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Integer data and CP14 writes Noncac
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9.4 AXI data read/write transaction
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Noncacheable, or strongly ordered,
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Noncacheable store word Noncacheabl
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LA Last Access External Memory Inte
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10.1 Clock domains 10.1.1 AXI clock
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10.2 Reset domains 10.2.1 Power-on
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REFCLK (PLL input) nPORESET ARESETn
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10.3 Power control 10.3.1 Dynamic p
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Clock, Reset, and Power Control the
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ATB APB I/O clamp I/O clamp L/S = L
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ATB APB I/O clamp I/O clamp LS = Le
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Clock, Reset, and Power Control 3.
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Powering up the debug and ETM domai
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7. Perform a normal software reset
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Clock, Reset, and Power Control 5.
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Chapter 11 Design for Test This cha
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In L1 MBIST Instruction Register Fi
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Note Do not test the CAMBIST arrays
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• number of rows of the L2 data,
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Design for Test Not all row setting
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In Design for Test Figure 11-4 show
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Design for Test When testing the ta
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CLK ARESETn MBISTMODE MBISTSHIFT MB
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End-of-test datalog retrieval Desig
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Pattern N RWRXMARCH 8N Row-fast Sta
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4. rscan array, data_seed = invert.
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3. R_, W, R, decr. 4. rscan data fr
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• the data after pass 1 of XADDRB
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(1 + (2 17)) 2 17 = 4,587,520 cycle
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processor input ports WEXTEST WINTE
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Design for Test toggling during shi
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12.1 Debug systems 12.1.1 Debug hos
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12.2.3 Security extensions and debu
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Instruction Mnemonic Description 12
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12.3.6 Power domains and debug 12.3
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Table 12-5 shows the APB interface
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12.4 Debug register descriptions Te
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MRC p14, 0, , c0, c0, 0 ; Read Debu
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31 30 29 28 27 26 25 24 23 22 21 20
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Bits Field Function [21:20] DTR acc
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Bits Field Function To access the D
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12.4.7 Watchpoint Fault Address Reg
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Bits Access Normal address [2] RW V
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12.4.12 Debug Run Control Register
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Table 12-23 shows how the bit value
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BVR[22:20] Meaning b011 The corresp
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Bits Field Function [15:14] Secure
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12.4.18 Operating System Lock Statu
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Debug • The sequence can be aband
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12.5 Management registers Offset Th
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Offset Register number Mnemonic Fun
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Bits Field Function [5] nDMAIRQ nDM
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12.5.7 Claim Tag Clear Register 12.
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12.5.10 Authentication Status Regis
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Table 12-45 shows fields that are i
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12.6 Debug events 12.6.1 Software d
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12.6.5 Watchpoint debug events If a
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Table 12-53 shows the values in the
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12.8 Debug state 12.8.1 Entering de
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12.8.4 Writing to the CPSR in debug
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Mode SCR[0] For CP15 instructions,
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12.8.9 Leaving debug state Imprecis
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12.9.3 Cache usage profiling Debug
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Note DBGPWRDWNREQ must be tied LOW
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If software running on the processo
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Rules for accessing the DCC At the
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} While the processor is running, i
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Debug Table 12-59 Values to write t
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12.11.4 Debug state entry Example 1
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} // Step 1. Update the CPSR value
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Writing the CPSR in debug state Exa
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Debug Example 12-21 Reading a word
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} // Step 9. Check for aborts. abor
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12.12 Debugging systems with energy
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MOV r0, r4 POP {r4, pc} Example 12-
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Chapter 13 NEON and VFP Programmers
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13.2 General-purpose registers 13.2
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13.3 Short vectors 13.3.1 About reg
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13.3.2 Operations using register ba
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NEON and VFP Programmers Model The
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Note All hardware ID information is
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Bits Field Function [12:8] - Reserv
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NEON and VFP Programmers Model Tabl
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13.6 Compliance with the IEEE 754 s
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Underflow NEON and VFP Programmers
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14.1 About the ETM 14.1.1 ETM featu
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14.1.3 NEON Bridge and bus matrix A
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14.3 ETM register summary The ETM r
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Bits Field Function [11:8] Major ET
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14.4.4 Peripheral Identification Re
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See the ETM Architecture Specificat
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Embedded Trace Macrocell Table 14-1
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14.5.3 Enabling events 14.5.4 Addre
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14.7 Context ID tracing Embedded Tr
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14.9 Idle state control Embedded Tr
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Chapter 15 Cross Trigger Interface
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CTICHIN[0] CTICHIN[1] CTICHIN[2] CT
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15.2 Trigger inputs and outputs Tri
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15.3 Connecting asynchronous channe
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15.5 CTI register summary Address o
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15.6 CTI register descriptions This
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15.6.4 CTI Application Trigger Clea
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Table 15-10 shows how the bit value
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15.6.12 ASIC Control Register, ASIC
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15.7 CTI Integration Test Registers
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15.7.4 ITTRIGOUTACK, 0xEF0 15.7.5 I
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Cross Trigger Interface Table 15-26
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15.8.3 Device Type Identifier, 0xFC
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Cross Trigger Interface Table 15-31
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16.1 About instruction cycle timing
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Page 497 and 498: Table 16-4 shows the operation of m
Page 499 and 500: Table 16-9 shows the operation of l
Page 501 and 502: d. See Load/store instructions on p
Page 503 and 504: Instruction Cycle Timing Table 16-1
Page 505 and 506: 16.4 Other pipeline-dependent laten
Page 507 and 508: 16.4.5 Conditional instructions Ins
Page 509 and 510: 16.6 Instruction-specific schedulin
Page 511 and 512: Instruction Cycle Timing VNEG Dd,Dm
Page 513 and 514: VMLA a VMLS a VMLAa VMLSa VQDMLAa V
Page 515 and 516: VSLI VSRI 16.6.5 Advanced SIMD floa
Page 517 and 518: 16.6.6 Advanced SIMD byte permute i
Page 519 and 520: Instruction Table 16-23 shows the o
Page 521 and 522: Instruction VST3 3-reg (unaligned)
Page 523 and 524: Instruction VLD3 3-reg (unaligned)
Page 525 and 526: Instruction Single precision cycles
Page 527 and 528: • FMACS, FNMACS • FMSCS, FNMSCS
Page 529 and 530: is dual issued with previous instru
Page 531 and 532: 17.1 About setup and hold times AC
Page 533 and 534: 17.2 AXI interface Table 17-2 shows
Page 535 and 536: 17.3 ATB and CTI interfaces Table 1
Page 537 and 538: AC Characteristics Table 17-4 Timin
Page 539 and 540: 17.6 L2 preload interface AC Charac
Page 541 and 542: 17.8 Miscellaneous signals AC Chara
Page 543 and 544: A.1 AXI interface Signal Descriptio
Page 545: A.3 MBIST and DFT interface A.3.1 M
Page 549 and 550: A.6 Miscellaneous signals Table A-7
Page 551 and 552: Signal I/O Reset Description CFGNMF
Page 553 and 554: Signal I/O Reset Description DBGNOP
Page 555 and 556: Appendix B Instruction Mnemonics Th
Page 557 and 558: Instruction Mnemonics Table B-1 Adv
Page 559 and 560: Appendix C Revisions This appendix
Page 561 and 562: Revisions Added text to clarify des
Page 563 and 564: Glossary This glossary describes so
Page 565 and 566: Glossary Automatic Test Pattern Gen
Page 567 and 568: Big-endian memory Memory in which:
Page 569 and 570: Conditional execution Glossary incl
Page 571 and 572: Glossary Embedded Trace Macrocell (
Page 573 and 574: Illegal instruction An instruction
Page 575 and 576: Glossary NaN Not a number. A symbol
Page 577 and 578: Glossary Significand The component
Page 579 and 580: Glossary Watchpoint A watchpoint is
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