Cortex-A8 Technical Reference Manual - ARM Information Center

Cache control and
configuration
L2 cache
PreLoad Engine
(PLE) control and
configuration
L2 cache PLE
control and
configuration
L1 instruction
and data cache,
and TLB Debug
3.1.2 System control and configuration
Cache Type c0, Cache Type Register on page 3-20
Cache Level Identification c0, Cache Level ID Register on page 3-39
System Control Coprocessor
Cache Size Identification c0, Cache Size Identification Registers on page 3-41
Cache Size Selection c0, Cache Size Selection Register on page 3-43
Cache operations c7, Cache operations on page 3-68
PLE Identification and Status c11, PLE Identification and Status Registers on page 3-104
PLE User Accessibility c11, PLE User Accessibility Register on page 3-106
PLE Channel Number c11, PLE Channel Number Register on page 3-108
PLE Enable c11, PLE enable commands on page 3-109
PLE Control c11, PLE Control Register on page 3-109
PLE Internal Start Address c11, PLE Internal Start Address Register on page 3-112
PLE Internal End Address c11, PLE Internal End Address Register on page 3-113
PLE Channel Status c11, PLE Channel Status Register on page 3-114
PLE Context ID c11, PLE Context ID Register on page 3-116
L1 instruction and data cache, BTB,
GHB, and TLB Debug
c15, L1 system array debug data registers on page 3-124
L2 unified cache L2 unified cache c15, L2 system array debug data registers on page 3-136
System
performance
monitor
a. Returns device ID code.
Table 3-1 System control coprocessor register functions (continued)
Function Register/operation Reference to description
Performance monitoring c9, Performance Monitor Control Register on page 3-76 -
c9, Interrupt Enable Clear Register on page 3-91
The purpose of the system control and configuration registers is to provide overall management
of:
• Security Extensions behavior
• memory functionality
• interrupt behavior
• exception handling
• program flow prediction
• coprocessor access rights for CP0-CP13.
The system control and configuration registers also provide the processor ID. Some of the
functionality depends on how you set external signals at reset.
System control and configuration behaves in three ways:
• as a set of flags or enables for specific functionality
• as a set of numbers, values that indicate system functionality
• as a set of addresses for processes in memory.
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