Cortex-A8 Technical Reference Manual - ARM Information Center

Table 3-36 shows the results of attempted access for each mode.
To access the Instruction Set Attributes Register 4, read CP15 with:
MRC p15, 0, , c0, c2, 4 ; Read Instruction Set Attributes Register 4
3.2.20 c0, Instruction Set Attributes Registers 5-7
3.2.21 c0, Cache Level ID Register
Bits Field Function
System Control Coprocessor
Table 3-35 Instruction Set Attributes Register 4 bit functions (continued)
[11:8] Write-back instructions Indicates support for write-back instructions:
0x1 = The processor supports all defined write-back addressing modes.
[7:4] With-shift instructions Indicates support for with-shift instructions.
0x4 = The processor supports:
• shifts of loads and stores over the range LSL 0-3
• constant shift options
• register-controlled shift options.
[3:0] Unprivileged instructions Indicates support for Unprivileged instructions:
0x2 = The processor supports LDR{SB|B|SH|H}T.
Table 3-36 Results of access to Instruction Set Attributes Register 4 a
Secure privileged Nonsecure privileged Secure User Nonsecure User
Read Write Read Write Read Write Read Write
Data Undefined Data Undefined Undefined Undefined Undefined Undefined
a. An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessor
instruction is executed.
The purpose of the Instruction Set Attributes Registers 5-7 are reserved, and they read as
0x00000000.
The purpose of the Cache Level ID Register is to indicate the cache levels that are implemented.
The register indicates the level of unification, LoU, and the level of coherency, LoC. For
example, in the CortexA8 processor, the point where both data and instruction are unified is the
Level 2 cache, therefore, the LoU is 3'b001. The point where both data and instruction are
coherent is the AMBA AXI interface, therefore, the LoC is 3'b010.
The Cache Level ID Register is:
• a read-only register common for Secure and Nonsecure states
• accessible in privileged modes only.
Figure 3-16 on page 3-40 shows the bit arrangement of the Cache Level ID Register.
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