Cortex-A8 Technical Reference Manual - ARM Information Center

7.2 Cache organization
7.2.1 Cache control operations
7.2.2 Cache miss handling
7.2.3 Cache disabled behavior
7.2.4 Unexpected hit behavior
7.2.5 Cache parity error detection
Level 1 Memory System
Each cache is 4-way set associative of configurable size. They are physically tagged, and
virtually indexed for instruction and physically indexed for data. The cache sizes are
configurable with sizes of 16KB or 32KB. Both the instruction cache and the data cache are
capable of providing two words per cycle for all requesting sources. Data cache can provide four
words per cycle for NEON or VFP memory accesses.
The system control coprocessor, CP15, handles the control of the L1 memory system and the
associated functionality, together with other system wide control attributes. See Chapter 3
System Control Coprocessor for more information on CP15 registers.
The cache control operations that are supported by the processor are described in Chapter 3
System Control Coprocessor.
A cache miss results when a read access is not present in the cache. The caches perform critical
word-first cache refilling.
If you disable the cache then the cache is not accessed for reads or writes. This ensures that you
can achieve maximum power savings. It is therefore important that before you disable the cache,
all of the entries are cleaned to ensure that the external memory has been updated. In addition,
if the cache is enabled with valid entries in it then it is possible that the entries in the cache
contain old data. Therefore the cache must be completely cleaned and invalidated before being
disabled. Unlike normal reads and writes to the cache, cache maintenance operations are
performed even if the cache is disabled.
An unexpected hit is where the cache reports a hit on a memory location that is marked as
noncacheable or shared. The unexpected hit is ignored.
For writes, an unexpected cache hit does not result in the cache being updated.
The purpose of cache parity error detection is to increase the tolerance to memory faults.
Instruction cache data RAM parity error detection
The instruction cache RAM is written on cache linefills. Parity error detection is done on a
fetch-wide basis, that is, a parity error on any byte in a 64-bit fetch region causes a parity error
on the first instruction within that fetch. The detection of a parity error instruction cache RAM
causes the processor to return a Prefetch Abort.
When the processor executes the instruction:
• the address of the fetch containing the parity error is stored in the Instruction Fault
Address Register
• the Instruction Fault Status Register is set to indicate the presence of a parity error.
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