Cortex-A8 Technical Reference Manual - ARM Information Center

Debug
Locks The debugger or software running on the system might lock out different parts of
the register map so they cannot be accessed while the debug session is in certain
states.
Power down
The APB interface does not permit accesses to registers inside the core power
domain when the core powers down.
Privilege of memory access permission
When nonprivileged software tries to access the APB interface, the system ignores or generates
an abort response on the access. You must implement this restriction at the system level because
the APB protocol does not have a control signal for privileged or user access. You can choose
to have the system either ignore or abort the access. Although you can place additional
restrictions on the memory transactions that are permitted to access the APB interface, ARM
does not recommend this.
Locks permission
You can lock the APB interface so access to some debug registers is restricted. There are two
locks:
Software lock
The debug monitor can set this lock to prevent erratic software from modifying
debug registers settings. See the ARM Architecture Reference Manual for more
information. A debug monitor can also set this lock prior to returning control to
the application, to reduce the chance of erratic code changing the debug settings.
When this lock is set, writes to all debug registers are ignored, except those writes
generated by the external debugger. See Lock Access Register on page 12-44 for
more information.
OS Lock An OS can set this lock on the debug register map so access to some debug
registers is not permitted while the OS is performing a save or restore sequence.
When this lock is set, the APB interface aborts accesses to registers in the core
power domain. See Operating System Lock Access Register on page 12-33 for
more information.
Note
• The state of these locks is held on debug power domain and, therefore, is not lost when
the core powers down.
• These locks are set to their reset values only on reset of the debug power domain
(PRESETn reset).
• Be sure to set the PADDR31 input signal to 1 for accesses originated from the external
debugger for the Software Lock override feature to work. See Table 12-5 on page 12-10
for more details.
• If you access a reserved or unused register while any lock is set to 1, it is Unpredictable
whether or not the APB interface generates an error response.
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