Cortex-A8 Technical Reference Manual - ARM Information Center

Glossary
NaN Not a number. A symbolic entity encoded in a floating-point format that has the maximum
exponent field and a nonzero fraction. An SNaN sets the Invalid Operation Cumulative (IOC)
flag if used in an arithmetic instruction and the instruction returns a QNaN. A QNaN propagates
through almost every arithmetic operation without signaling exceptions and has a most
significant fraction bit of one.
PA See Physical Address.
Penalty The number of cycles in which no useful Execute stage pipeline activity can occur because an
instruction flow is different from that assumed or predicted.
Power-on reset See Cold reset.
Prefetching In pipelined processors, the process of fetching instructions from memory to fill up the pipeline
before the preceding instructions have finished executing. Prefetching an instruction does not
mean that the instruction has to be executed.
Prefetch Abort An indication from a memory system to the core that an instruction has been fetched from an
illegal memory location. An exception must be taken if the processor attempts to execute the
instruction. A Prefetch Abort can be caused by the external or internal memory system as a
result of attempting to access invalid instruction memory.
See also Data Abort, External Abort and Abort.
Processor A processor is the circuitry in a computer system required to process data using the computer
instructions. It is an abbreviation of microprocessor. A clock source, power supplies, and main
memory are also required to create a minimum complete working computer system.
Physical Address (PA)
RAZ See Read-As-Zero.
The MMU performs a translation on Modified Virtual Addresses (MVA) to produce the Physical
Address (PA) that is given to the AMBA bus to perform an external access. The PA is also stored
in the data cache to avoid the necessity for address translation when data is cast out of the cache.
See also Fast Context Switch Extension.
Read-As-Zero (RAZ) Appear as zero when read.
Read Reads are defined as memory operations that have the semantics of a load. That is, the ARM
instructions LDM, LDRD, LDC, LDR, LDRT, LDRSH, LDRH, LDRSB, LDRB, LDRBT,
LDREX, RFE, STREX, SWP, and SWPB, and the Thumb instructions LDM, LDR, LDRSH,
LDRH, LDRSB, LDRB, and POP.
Java instructions that are accelerated by hardware can cause a number of reads to occur,
according to the state of the Java stack and the implementation of the Java hardware
acceleration.
RealView ICE A system for debugging embedded processor cores using a JTAG interface.
Region A partition of instruction or data memory space.
Remapping Changing the address of physical memory or devices after the application has started executing.
This is typically done to permit RAM to replace ROM when the initialization has been
completed.
Reserved A field in a control register or instruction format is reserved if the field is to be defined by the
implementation, or produces Unpredictable results if the contents of the field are not zero. These
fields are reserved for use in future extensions of the architecture or are
implementation-specific. All reserved bits not used by the implementation must be written as 0
and read as 0.
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