Cortex-A8 Technical Reference Manual - ARM Information Center

16.4 Other pipeline-dependent latencies
Instruction Cycle Timing
This section describes a variety of other factors that can affect the timing of a code sequence.
For the most part, these factors cannot be accurately predicted on a case by case basis, but can
be accounted for statistically if determining the overall timing for a larger section of code.
16.4.1 Cycle penalty for instruction flow change
Whenever a control flow change occurs in the processor that the prefetch unit has not predicted,
the pipeline must be flushed. This results in a cycle stall equal in number to the length of the
integer pipeline. This branch mispredict penalty is 13 cycles. See Chapter 5 Program Flow
Prediction for details on program execution prediction.
16.4.2 Memory system effects on instruction timings
Replay
event
Load data
miss
Data TLB
miss
Store
buffer full
Unaligned
load or
store
request
16.4.3 Thumb-2 instructions
Because the processor is a statically scheduled design, any stall from the memory system can
result in the minimum of a 8-cycle delay. This 8-cycle delay minimum is balanced with the
minimum number of possible cycles to receive data from the L2 cache in the case of an L1 load
miss. Table 16-16 gives the most common cases that can result in an instruction replay because
of a memory system stall.
Delay Description
Table 16-16 Memory system effects on instruction timings
8 cycles 1. A load instruction misses in the L1 data cache.
2. A request is then made to the L2 data cache.
3. If a miss also occurs in the L2 data cache, then a second replay occurs. The
number of stall cycles depends on the external system memory timing. The time
required to receive the critical word for an L2 cache miss is 18 core cycles plus
the number of cycles required by the external memory system. The minimum
number of additional cycles required for the external system is 2 cycles, making
the total minimum cycle count 20 cycles. However, 20 cycles are likely to be
optimistic because this can only occur in a system with a 1:1 bus ratio and zero
wait-state memory.
24 cycles 1. A table walk because of a miss in the L1 TLB causes a 24-cycle delay, assuming
the translation table entries are found in the L2 cache.
2. If the translation table entries are not present in the L2 cache, the number of stall
cycles depends on the external system memory timing.
8 cycles
plus latency
to drain fill
buffer
1. A store instruction miss does not result in any stalls unless the store buffer is
full.
2. In the case of a full store buffer, the delay is at least eight cycles. The delay can
be more if it takes longer to drain some entries from the store buffer.
8 cycles 1. If a load instruction address is unaligned and the full access is not contained
within a 128-bit boundary, there is a 8-cycle penalty.
2. If a store instruction address is unaligned and the full access is not contained
within a 64-bit boundary, there is a 8-cycle penalty.
As a general rule, Thumb-2 instructions are executed with timing constraints identical to their
ARM counterparts. However, there are some second order effects to the cycle timing that you
must observe. First, the code footprint is smaller, which can reduce the number of instruction
cache misses and therefore reduce the cycle count. Second, branch instructions tend to be more
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