Cortex-A8 Technical Reference Manual - ARM Information Center

System Control Coprocessor
Figure 3-33 c7 format for MVA
Table 3-77 shows how the bit values correspond with the Cache Operation functions for MVA
format operations.
SBZ
31 6 5 0
The value supplied Should-Be-Zero. The value 0x00000000 must be written to the register.
VA to PA translation operations
The purpose of the VA to PA translation operations, nonsecure operations, is to provide a secure
means to determine address translation between the Secure and Nonsecure states. VA to PA
translations operate through:
• PA Register
• VA to PA translation in the current Secure or Nonsecure state on page 3-73
• VA to PA translation in the other Secure or Nonsecure state on page 3-74.
PA Register
Modified virtual address Reserved
Bits Field Function
The purpose of the Physical Address Register (PAR) is to hold:
• the Physical Address (PA) after a successful translation
• the source of the abort for an unsuccessful translation.
Table 3-78 on page 3-72 shows the purpose of the bits of the PAR for successful translations and
Table 3-79 on page 3-73 shows the purpose of the bits of the PAR for unsuccessful translations.
The PAR is:
• a read/write register banked in Secure and Nonsecure states
• accessible in privileged modes only.
Table 3-77 Functional bits of c7 for MVA
[31:6] Modified virtual address Specifies address to invalidate, clean, or prefetch
[5:0] - Reserved, SBZ
Figure 3-34 shows the bit arrangement of the PAR for successful translations.
31 12 11 10 9 8 7 6 4 3 2 1 0
PA P INNER
0
Reserved SH
NS
Supersection
OUTER
Figure 3-34 PA Register format for successful translation
Figure 3-35 on page 3-72 shows the bit arrangement of the PAR for unsuccessful translations.
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