Cortex-A8 Technical Reference Manual - ARM Information Center

• accessible in privileged modes only.
Figure 3-6 shows the bit arrangement of the Debug Feature Register 0.
System Control Coprocessor
31 24 23 20 19 16 15 12 11 8 7 4 3 0
Reserved
Microcontroller debug model – memory-mapped
Trace debug model – memory-mapped
Trace debug model – coprocessor-based
Core debug model – memory-mapped
Secure debug model – coprocessor-based
Core debug model – coprocessor-based
Figure 3-6 Debug Feature Register 0 format
Table 3-16 shows how the bit values correspond with the Debug Feature Register 0 functions.
Bits Field Function
[31:24] - Reserved, RAZ.
[23:20] Microcontroller
debug model –
memory-mapped
[19:16] Trace debug model –
memory-mapped
[15:12] Trace debug model –
coprocessor-based
[11:8] Core debug model –
memory mapped
[7:4] Secure debug model –
coprocessor-based
[3:0] Core debug model –
coprocessor-based
Table 3-17 shows the results of attempted access for each mode.
To access the Debug Feature Register 0, read CP15 with:
Table 3-16 Debug Feature Register 0 bit functions
Indicates support for the microcontroller debug model:
0x0 = Processor does not support the microcontroller debug
model – memory-mapped.
Indicates support for the trace debug model – memory-mapped:
0x1 = Processor supports the trace debug model – memory-mapped
0x0 = Processor does not support the trace debug model – memory-mapped. a
Indicates support for the coprocessor-based trace debug model:
0x0 = Processor does not support the trace debug model – coprocessor.
Indicates support for the memory-mapped debug model:
0x4 = Processor supports the memory mapped debug model.
Indicates support for the secure debug model – coprocessor:
0x0 = Processor does not support the secure debug model – coprocessor.
Indicates support for the coprocessor debug model:
0x0 = Processor does not support the coprocessor debug model.
a. A value of 0x0 indicates that the ETM option is not configured for the processor, see Configurable options on page 1-10
Table 3-17 Results of access to Debug Feature Register 0 a
Secure privileged Nonsecure privileged Secure User Nonsecure User
Read Write Read Write Read Write Read Write
Data Undefined Data Undefined Undefined Undefined Undefined Undefined
a. An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessor
instruction is executed.
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