Cortex-A8 Technical Reference Manual - ARM Information Center

11.1 MBIST
11.1.1 About MBIST
11.1.2 MBIST registers
This section describes the array architecture and operation of the MBIST:
• About MBIST
• MBIST registers
• MBIST operation on page 11-14
• Pattern selection on page 11-18.
The processor has three separate MBIST controllers:
Design for Test
L1 and L2 MBIST controllers
The L1 and L2 MBIST controllers communicate with RAM arrays distributed
around the chip. Their controls are directly ported to the interface for use with
external testbench or Automated Test Equipment (ATE) drivers.
CAMBIST controller
The CAMBIST controller is a slave of the L1 MBIST controller. It targets the
comparator logic of the Content-Addressable Memory (CAM). The L1 MBIST
controller tests the contents of the I-CAM and D-CAM arrays.
The following arrays require MBIST support:
• Instruction cache (I-cache)
• Data cache (D-cache)
• Global History Buffer (GHB)
• Branch Target Buffer (BTB)
• Translation Look-aside Buffer (TLB)
Note
The TLB has separate instruction and data arrays, each containing an attribute array, a
CAM array, and a Physical Address (PA) array.
• Hash Virtual Address Buffer (HVAB)
• L1 tag RAM
• all L2 cache RAM such as data, parity, tag, and valid RAMs.
Table 11-1 shows the MBIST registers. See Figure 11-7 on page 11-15 for information about the
timing of an MBIST instruction load.
Register Access Reference
Table 11-1 MBIST register summary
L1 MBIST Instruction Register W See L1 MBIST Instruction Register on page 11-3
L2 MBIST Instruction Register W See L2 MBIST Instruction Register on page 11-6
L1 and L2 MBIST GO-NOGO
Instruction Registers
W See L1 and L2 MBIST GO-NOGO Instruction
Registers on page 11-10
L1 MBIST Datalog Register R See L1 MBIST Datalog Register on page 11-11
L2 MBIST Datalog Register R See L2 MBIST Datalog Register on page 11-12
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