Cortex-A8 Technical Reference Manual - ARM Information Center

12.12 Debugging systems with energy management capabilities
12.12.1 Standby
12.12.2 Emulating power down
Debug
The processor offers functionality for debugging systems with energy management capabilities.
This section describes scenarios where the OS takes energy-saving measures when in an idle
state.
The different measures that the OS can take to save energy during an idle state are divided into
two groups:
Standby The OS takes measures that reduce energy consumption but maintain the
processor state.
Power down The OS takes measures that reduce energy consumption but do not maintain the
processor state. Recovery involves a reset of the core after the power level has
been restored, and reinstallation of the processor state.
Standby is the least invasive OS energy saving state because it only implies that the core is
unavailable. It does not clear any of the debug settings. For this case, if DBGNOCLKSTOP is
HIGH, the processor guarantees the following:
• If the processor is in standby and a halting debug event occurs, the processor:
— leaves standby
— retires the Wait-For-Interrupt (WFI) instruction
— enters debug state.
• The processor responds to APB accesses as if it was not in standby.
Note
If you implement the CoreSight Debug Access Port (DAP) in your system, ARM recommends
that the DAP CDBGPWRUPREQ output is connected to the DBGNOCLKSTOP processor
input.
By writing to bit [0] of the PRCR, the debugger asserts the DBGNOPWRDWN output. The
expected usage model of this signal is that it is connected to the system power controller and
that, when HIGH, it indicates that this controller can work in emulate mode.
If on a power-down request from the processor, the power controller is in emulate mode. It does
not remove core or ETM power but, otherwise, it behaves exactly the same as in normal mode.
Emulating power down is ideal for debugging applications running on top of operating systems
that are free of errors because the debug register settings are not lost on a power-down event.
However, there are a number of disadvantages such as:
• nIRQ and nFIQ interrupts to the processor must be externally masked as part of the
emulation to prevent them from retiring the WFI instruction from the pipeline.
• The reset controller must also be aware of this emulate mode to assert ARESETn on
power up, rather than nPORESET. Asserting nPORESET on power up clears the debug
registers inside the core power domain.
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