Cortex-A8 Technical Reference Manual - ARM Information Center

A.3.2 DFT pins and additional MBIST pin requirements during MBIST testing
Signal I/O
Signal Descriptions
Table A-4 shows the signals necessary for DFT. It also shows the additional pins required during
MBIST testing.
Value during
functional mode
Table A-4 DFT and additional MBIST pin requirements
Value during
MBIST mode
Description
MBISTMODEL1 I 0 1 Configures L1 for MBIST mode and disables
instruction fetch after reset.
MBISTMODEL2 I 0 1 Configures L2 for MBIST mode and disables
instruction fetch after reset.
TESTMODE I 0 0 Indicates ATPG test mode. Deassert during
MBIST mode.
TESTCGATE I 0 1 Controls core clock gating during test mode
or MBIST mode.
TESTEGATE I 0 0 Controls ETM clock gating. Deassert to save
power during MBIST mode.
TESTNGATE I 0 0 Controls NEON clock gating. Deassert to
save power during MBIST mode.
SE I 0 0 Scan enable signal. Ensures safe shifting of
scan chains.
SAFESHIFTRAMIF I 0 0 Prevents the RAM in the instruction fetch unit
from performing a write operation during
scan shifting.
SAFESHIFTRAMLS I 0 0 Prevents the RAM in the load/store unit from
performing a write operation during scan
shifting.
SAFESHIFTRAML2 I 0 0 Prevents the RAM in the L2 cache unit from
performing a write operation during scan
shifting.
SERIALTEST I 0 0 Concatenates the wrapper boundary register
scan cells into a single scan chain.
SHIFTWR I 0 0 IEEE 1500 standard shift signal.
CAPTUREWR I 0 0 IEEE 1500 standard capture signal.
WINTEST I 0 0 Enables internal testing during ATPG.
WEXTEST I 0 0 Enables external testing during ATPG.
WSE I 0 0 Wrapper scan enable. Enables serial shifting
of the wrapper scan chain.
PRESETn I - 0 Active-LOW APB reset input.
ACLKEN I - 1 AXI clock enable signal. This signal must be
driven HIGH for at least one clock cycle
during reset. The value after reset does not
affect the MBIST operation.
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