Cortex-A8 Technical Reference Manual - ARM Information Center

Mode
Updating CPSR bits
Debug
If the debugger writes to the CPSR a value so that it sets the CPSR[4:0] bits to a processor mode
where invasive debug is not permitted, this update of the CPSR[4:0] bits is ignored. Similarly,
if invasive debug is not permitted for privilege modes in the current security state, writes to the
CPSR privileged bits are ignored.
Table 12-55 shows which updates are permitted in debug state:
Secure state a or
Monitor mode
Writing to the CPSR SCR
While in debug state, if the debugger forces the processor to execute a CP15 MCR instruction
to write to the CP15 Secure Configuration Register (SCR), it is only permitted to execute if
either of these conditions is true:
• the processor is in a secure privileged mode including Monitor mode
• the processor is in secure User mode, and both DBGEN and SPIDEN are asserted.
Note
• Writes to the SCR while in nonsecure state are not permitted even if both DBGEN and
SPIDEN are asserted, except if the processor is in Monitor mode because it is considered
to be a secure privileged mode regardless of the value of the SCR[0] NS bit.
• The processor treats attempts to write to the SCR when they are not permitted as
Undefined instruction exceptions. See Exceptions in debug state on page 12-61 for details
of how the processor behaves when Undefined instruction exceptions occur while in
debug state.
Coprocessor instructions
Table 12-55 Permitted updates to the CPSR in debug state
DBGEN & SPIDEN
Modify CPSR[4:0]
to Monitor mode
The rules for executing coprocessor instructions other than CP14 and CP15 while in debug state
are the same as in normal state. CP14 debug instructions are always permitted while in debug
state regardless of the debug permissions, processor mode, and security state.
Note
Nondebug CP14 instructions behave as CP15 instructions while in debug state.
Update privileged
CPSR bits b
User Yes 0 Update ignored Update ignored
Privileged Yes 0 Permitted Permitted
Any No 0 Update ignored Permitted
Any X 1 Permitted Permitted
a. The processor is in secure state when CP15 SCR[0] nonsecure bit is set to 0.
b. This column excludes the case where the debugger attempts to change CPSR[4:0] to Monitor mode, that is, it
only includes updates of the A, I, or F bits, or the CPSR[4:0] bits to a mode other than Monitor.
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