Cortex-A8 Technical Reference Manual - ARM Information Center

Instruction L1
Data 0 register
To write one entry in the instruction side GHB array, for example:
System Control Coprocessor
Figure 3-80 GHB array write operation format
LDR R0, =0x3333AAAA;
MCR p15, 0, R0, c15, c1, 0; Move R0 to I-L1 Data 0 Register
LDR R1, =0x0000020C;
MCR p15, 0, R1, c15, c5, 2; Write I-L1 Data 0 Register to GHB
To read one entry in the instruction side GHB array, for example:
LDR R1, =0x0000020C;
MCR p15, 0, R1, c15, c7, 2; Read GHB into I-L1 Data 0 Register
MRC p15, 0, R0, c15, c1, 0; Move I-L1 Data 0 Register to R0
3.2.81 c15, L2 system array debug data registers
31 0
31 10 9 2 1
0
The purpose of the L2 system array debug data registers is to hold the data:
• that is returned from the L2 tag, data, parity/ECC read operations
• for L2 tag, data, parity/ECC write operations.
Because the L2 data arrays are greater than 32-bits wide, the processor contains three registers,
Data 0, Data 1, and Data 2 registers, to hold data when retrieving or registering data as a result
of read/write operations. If the data is greater than 32-bit wide, all of the registers are used to
transfer data.
The Data 0, Data 1, and Data 2 read/write registers are accessible in secure privileged modes
only.
To access the L2 system debug registers, read or write CP15 with:
MCR p15, 0, , c15, c8, 0 ; Write L2 Data 0 Register
MRC p15, 0, , c15, c8, 0 ; Read L2 Data 0 Register
MCR p15, 0, , c15, c8, 1 ; Write L2 Data 1 Register
MRC p15, 0, , c15, c8, 1 ; Read L2 Data 1 Register
MCR p15, 0, , c15, c8, 5 ; Write L2 Data 2 Register
MRC p15, 0, , c15, c8, 5 ; Read L2 Data 2 Register
Figure 3-81 on page 3-137 shows the bit arrangement of the L2 Data 0 Register when retrieving
or registering data as a result of the read/write operations.
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Data
Reserved Address
Address
Reserved
Write data
GHB
array