Cortex-A8 Technical Reference Manual - ARM Information Center

ATB
APB
I/O clamp
I/O clamp
L/S = Level Shift
ETM
(ATCLK)
Debug
L/S
Clamp+L/S
Clamp+L/S
Clamp
I/O clamp
AXI
ETM
(CLK)
L1 I$ RAM
BTB RAM
GHB RAM
Clock, Reset, and Power Control
Figure 10-12 Retention power domains
Similarly, the L1 data cache can be placed on a separate power domain from the rest of the
processor. This L1 data cache power domain can be shared with the L2. However, sharing of the
two cache power domains is not required. In addition, all inputs into the L1 data cache RAMs
such as tag, HVAB, and data RAMs must be clamped to safe values to avoid corrupting the data
when entering or exiting a power-down state.
Note
Data retention within the L1 instruction cache is not supported.
Power cycle the core with L2 cache retaining state
A power down and reset sequence of the processor with the L2 cache retained is as follows:
1. Clean to the point of unification the L1 data cache.
2. Save off any TLB state such as locked entries, if required.
3. Save off architectural state, if required.
Integer core
L/S Clamp+L/S
4. Assert L2RSTDISABLE to disable L2 hardware reset.
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Clamp
NEON
L1 D$ RAM
Clamp
L/S
L/S
Clamp+L/S
L2 cache
RAM