Cortex-A8 Technical Reference Manual - ARM Information Center

12.4.4 CP14 c0, Debug Self Address Offset Register
Debug
The Debug Self Address Offset Register is a read-only register that returns a 20-bit offset value
from the Debug ROM Address Register to the physical address of the processor debug registers.
The address read from this register depends on the DBGSELFADDR[31:12] and
DBGSELFADDRV inputs. DBGSELFADDRV must be tied off to 1 if
DBGSELFADDR[31:12] is tied off to a valid value.
The Debug Self Address Offset Register is:
• in CP14 c0
• a read-only register
• accessible in User and privileged modes.
Figure 12-4 shows the bit arrangement of the Debug Self Address Offset Register.
Figure 12-4 Debug Self Address Offset Register format
Table 12-13 shows how the bit values correspond with the Debug Self Address Offset Register
functions.
Bits Field Function
[31:12] Debug bus
self-address
offset value
To access the Debug Self Address Offset Register, read CP14 c0 with:
MRC p14, 0, , c2, c0, 0 ; Read Debug Self Address Offset Register
12.4.5 CP14 c1, Debug Status and Control Register
31 12 11 2 1 0
[11:2] - Reserved. RAZ, SBZP.
Debug bus self-address offset value Reserved
The DSCR is a read-only register that contains status and control information about the debug
unit. Figure 12-5 on page 12-16 shows the bit arrangement of the DSCR.
Note
For the APB interface, the DSCR is a read/write register.
Valid bits
Table 12-13 Debug Self Address Offset Register bit functions
Indicates bits [31:12] of the 2’s complement offset from the debug ROM physical address
to the physical address of the start of the region where the debug registers are mapped. The
value read by this field corresponds to the value of DBGSELFADDR[31:12].
[1:0] Valid bits Reads b11 if DBGSELFADDRV is set to 1, reads b00 otherwise. DBGSELFADDRV must
be set to 1 if DBGSELFADDR[31:12] is set to a valid value.
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