Cortex-A8 Technical Reference Manual - ARM Information Center

31 27 26 22 21
0
Reserved
L1 Data 0
register
L1 Data 1
register
Address
System Control Coprocessor
Figure 3-69 L1 TLB CAM read operation format
Figure 3-70 shows the bit arrangement of the L1 TLB CAM write operations.
TLB CAM array examples
Reserved
To write one entry in data side TLB CAM array, for example:
Figure 3-70 L1 TLB CAM write operation format
LDR R0, =0x03000323;
MCR p15, 0, R0, c15, c0, 0; Move R0 to D-L1 Data 0 Register
LDR R2, =0x01;
MCR p15, 0, R2, c15, c0, 1; Move R0 to D-L1 Data 1 Register
LDR R1, =0x00C00000;
MCR p15, 0, R1, c15, c0, 2; Write D-L1 Data 0 or 1 Register to D-TLB CAM
To read one entry in data side TLB CAM array, for example:
LDR R1, =0x00C00000;
MCR p15, 0, R1, c15, c2, 2; Read D-TLB CAM into data L1 Data 0/1 Register
MRC p15, 0, R0, c15, c0, 0; Move D-L1 Data 0 Register to R0
MRC p15, 0, R2, c15, c0, 1; Move D-L1 Data 1 Register to R2
To write one entry in instruction side TLB CAM array, for example:
LDR R0, =0x03000323;
MCR p15, 0, R0, c15, c1, 0; Move R0 to I-L1 Data 0 Register
LDR R2, =0x01;
MCR p15, 0, R2, c15, c1, 1; Move R0 to I-L1 Data 1 Register
LDR R1, =0x00C00000;
MCR p15, 0, R1, c15, c1, 2; Write I-L1 Data 0 or 1 Register to D-TLB CAM
To read one entry in instruction side TLB CAM array, for example:
Address
31 0
31 27 26 22 21
0
Reserved
Address
LDR R1, =0x00C00000;
MCR p15, 0, R1, c15, c3, 2; Read I-TLB CAM into data L1 Data 0/1 Register
MRC p15, 0, R0, c15, c1, 0; Move I-L1 Data 0 Register to R0
MRC p15, 0, R2, c15, c1, 1; Move I-L1 Data 1 Register to R2
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Data
Data
Reserved
Address
Write data
TLB
array
TLB
array