Cortex-A8 Technical Reference Manual - ARM Information Center

3.2.32 c2, Translation Table Base Register 1
System Control Coprocessor
A write to the Translation Table Base Register 0 updates the address of the first level translation
table from the value in bits [31:7] of the written value, to account for the maximum value of 7
for N. The number of bits of this address that the processor uses, and the required alignment of
the first level translation table, depends on the value of N, see c2, Translation Table Base
Control Register on page 3-60.
A read from the Translation Table Base Register 0 returns the complete address of the first level
translation table in bits [31:7] of the read value, regardless of the value of N.
To access the Translation Table Base Register 0, read or write CP15 c2 with:
MRC p15, 0, , c2, c0, 0 ; Read Translation Table Base Register
MCR p15, 0, , c2, c0, 0 ; Write Translation Table Base Register
Note
The processor cannot perform a translation table walk from L1 cache. Therefore, if C is set to
1, to ensure coherency, you must store translation tables in inner write-through memory. If you
store the translation tables in an inner write-back memory region, you must clean the
appropriate cache entries after modification so that the mechanism for the hardware translation
table walks sees them.
The purpose of the Translation Table Base Register 1 is to hold the physical address of the first
level table. The expected use of the Translation Table Base Register 1 is for OS and I/O
addresses.
The Translation Table Base Register 1 is:
• a read/write register banked for Secure and Nonsecure states
• accessible in privileged modes only.
Figure 3-27 shows the bit arrangement of the Translation Table Base Register 1.
31 14 13 5 4 3 2 1 0
Translation table base 1
Reserved
Figure 3-27 Translation Table Base Register 1 format
Table 3-62 shows how the bit values correspond with the Translation Table Base Register 1
functions.
Bits Field Function
[31:14] Translation table
base 1
[13:5] - Reserved. RAZ, SBZ.
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RGN
P
S C
Table 3-62 Translation Table Base Register 1 bit functions
Holds the translation table base address, the physical address of the first level translation
table.
[4:3] RGN Indicates the outer cacheable attributes for translation table walking:
b00 = outer noncacheable
b01 = write-back, write allocate
b10 = write-through, no allocate on write
b11 = write-back, no allocate on write.