Cortex-A8 Technical Reference Manual - ARM Information Center

TL bit
value
3.2.57 c10, TLB preload operation
For the Data or Instruction TLB Lockdown Register:
System Control Coprocessor
• The TLB lockdown behavior depends on the TL bit, see c1, Nonsecure Access Control
Register on page 3-56. If the TL bit is not set to 1, the lockdown entries are reserved for
the Secure state.
• The TLB Lockdown Register must be used with the TLB preload operation. See c10, TLB
preload operation.
Note
Setting the P bit before a hardware translation table walk does not guarantee the locking down
of an entry. The Base field must be set to the first unlocked entry. The Victim field must always
be set to a value greater than or equal to the value of the Base field.
Table 3-111 shows the results of attempted access for each mode.
To access the Data TLB Lockdown Register, read or write CP15 with:
MRC p15, 0, , c10, c0, 0 ; Read Data TLB Lockdown Register
MCR p15, 0, , c10, c0, 0 ; Write Data TLB Lockdown Register
To access the Instruction TLB Lockdown Register, read or write CP15 with:
MRC p15, 0, , c10, c0, 1 ; Read Instruction TLB Lockdown Register
MCR p15, 0, , c10, c0, 1 ; Write Instruction TLB Lockdown Register
The TLB preload operations are used to load entries into either the instruction or data TLB as
specified by the virtual address. The operation performs a TLB lookup to determine if the virtual
address has been cached in the TLB array. If the TLB lookup misses in the TLB array, a
hardware translation table walk is performed. There are two possible results of the hardware
translation table walk:
• the descriptor is cached in the TLB array at the entry specified by the Victim field in the
TLB Lockdown Register
• the descriptor faults.
Table 3-111 Results of access to the TLB Lockdown Register a
Secure privileged Nonsecure privileged Secure User Nonsecure User
Read Write Read Write Read Write Read Write
0 Data Data Undefined Undefined Undefined Undefined Undefined Undefined
1 Data Data Data Data Undefined Undefined Undefined Undefined
a. An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessor
instruction is executed.
If the operation is a preload D-TLB instruction and the descriptor faults, a data abort is
indicated. The DFSR and DFAR indicate the fault type and the fault address, respectively.
If the operation is a preload I-TLB instruction and the descriptor faults, a data abort is indicated.
The DFSR indicates the instruction cache maintenance fault value. The DFAR contains the
faulty virtual address, and the IFSR contains the fault type encoding.
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