Cortex-A8 Technical Reference Manual - ARM Information Center

8.2 Cache organization
8.2.1 L2 cache bank structure
8.2.2 L2 cache transfer policy
Level 2 Memory System
The L2 cache is 8-way set associative of configurable size. The cache is physically addressed.
The cache sizes are configurable with sizes in the range of 0KB, 128KB, 256KB, 512KB, and
1MB.
You can reduce the effective cache size using lockdown format C. This feature enables you to
lock cache ways to prevent allocation to locked entries.
You can configure the L2 memory pipeline to insert wait states to take into account the latencies
of the compiled memories for the implemented RAMs.
To enable streaming of NEON read accesses from the L1 data cache, the L2 memory system
supports up to twelve NEON read accesses. The write buffer handles integer writes, NEON
writes, and eviction accesses from the L1 data cache. This enables streaming of write requests
from the L1 data cache.
The L2 cache incorporates a dirty bit per quadword to reduce AXI traffic. This eliminates
unnecessary transfer of clean data on the AXI interface.
The L2 cache is partitioned into multiple banks to enable parallel operations. There are two
levels of banking:
• the tag array is partitioned into multiple banks to enable up to two requests to access
different tag banks of the L2 cache simultaneously
• each tag bank is partitioned into multiple data banks to enable streaming accesses to the
data banks.
Figure 8-1 shows the logical representation of the L2 cache bank structure. The diagram shows
a configuration with all possible tag and data bank combinations.
Data bank
selected by
PA[5:4]
Data bank 3
Data bank 2
Data bank 1
Data bank 0
Tag bank 0
Figure 8-1 L2 cache bank structure
Table 8-1 on page 8-4 describes instruction and data transfers to and from the L2 cache.
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b11
b10
b01
b00
Tag bank selected by PA[6]
b0
b1
Data bank 3
Data bank 2
Data bank 1
Data bank 0
Tag bank 1
128KB - 1MB 2 tag, 4 data