Cortex-A8 Technical Reference Manual - ARM Information Center

1.3 Components of the processor
L1
RAM
L2
cache
1.3.1 Instruction fetch
The main components of the processor are:
• Instruction fetch
• Instruction decode on page 1-5
• Instruction execute on page 1-5
• Load/store on page 1-5
• L2 cache on page 1-5
• NEON on page 1-6
• ETM on page 1-6.
Figure 1-1 shows the structure of the Cortex-A8 processor.
DFT interface APB interface
Instruction fetch
L1 cache
interface
Fill and eviction queue
BIU
TLB
Arbitration
AXI interface
Prefetch
and
branch
prediction
Write
buffer
Instruction decode Instruction execute
Decode &
sequencer
Dependency
check and
issue
Instruction, data, NEON and preload engine buffers
L2 cache pipeline control
Parity and
L2 cache data RAM L2 cache tag RAM
ECC RAM
Introduction
Cortex-A8
Figure 1-1 Cortex-A8 block diagram
The instruction fetch unit predicts the instruction stream, fetches instructions from the L1
instruction cache, and places the fetched instructions into a buffer for consumption by the
decode pipeline. The instruction fetch unit also includes the L1 instruction cache.
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Flags
RegBank
ALU1
ALU2
MAC
Control
NEON
ATB interface
ETM
Load/store
L1
cache
interface
TLB
L1
RAM