Cortex-A8 Technical Reference Manual - ARM Information Center

Clock, Reset, and Power Control
the processor asserts CLKSTOPACK, it closes the architectural clock gate. However, eight
CLK cycles must pass before you can rely on the architectural clock gate being completely
closed.
Figure 10-9 on page 10-9 shows the system stopping CLK after the architectural clock gate is
closed. This enables additional energy savings, but it is optional. In addition, the supply voltage,
Vdd (core) can also be lowered as shown in Figure 10-9 on page 10-9 to improve energy
savings. However, CLK must not stop before the architectural clock gate is closed, that is, it
must continue to run for at least eight cycles after CLKSTOPACK is asserted.
After the architectural clock gate closes, the system can keep the processor in this low-power
state for as long as required, by holding CLKSTOPREQ HIGH. When the system deasserts
CLKSTOPREQ, this causes the architectural clock gate to open. The processor then responds
by deasserting CLKSTOPACK and resuming instruction execution. The upper bound for the
number of CLK cycles between CLKSTOPREQ and CLKSTOPACK deassertion is 8.
When driving CLKSTOPREQ, the system must comply with a set of protocol rules, otherwise
the processor behavior is Unpredictable. The rules are as follows:
• CLKSTOPREQ must not transition from LOW to HIGH if CLKSTOPACK is already
HIGH.
• When CLKSTOPREQ is HIGH, it must remain HIGH until CLKSTOPACK goes
HIGH. Only when CLKSTOPACK goes HIGH can CLKSTOPREQ go LOW.
Note
• If you are debugging software running on the Cortex-A8 processor, DBGNOCLKSTOP
must be HIGH. Otherwise, halting debug events do not work as architected and the APB
interface does not return a response when accessing the ETM, CTI, or core domain debug
registers. See Table 12-3 on page 12-6 for information on the debug registers that are in
the core.
• If DBGNOCLKSTOP is HIGH and the system asserts CLKSTOPREQ, the processor
goes into an idle state but not into a low-power state.
• The CLKSTOPACK output pin remains HIGH even when DBGNOCLKSTOP is
HIGH.
NEON or ETM unit level gating
In addition to the architectural gating mechanism, the processor supports gating of major
components within the processor such as the NEON unit, VFP coprocessor, and ETM unit.
The cp10 and cp11 fields in the CP15 c1 Coprocessor Access Control Register control access to
the NEON and VFP coprocessor. See c1, Coprocessor Access Control Register on page 3-52.
Reset clears the cp10 and cp11 fields. If there are no NEON or VFP instructions in the pipeline,
the clock is disabled for lower power.
You can also disable the NEON unit and VFP coprocessor by setting the EN bit of the
Floating-point Exception Register to 0. See Floating-point Exception Register, FPEXC on
page 13-14.
The ETM Control Register enables the ETM. See the Embedded Trace Macrocell Architecture
Specification for more information. The global enable bit in the CTI Control Register enables
the ETM clocks, excluding the ATB clock, ATCLK, that can only be gated external to the
processor. See CTI Control Register, CTICONTROL on page 15-11.
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