Cortex-A8 Technical Reference Manual - ARM Information Center

System Control Coprocessor
Table 3-112 describes the behavior of memory accesses when the region remapped registers,
PRRR and NMRR, are applied.
Table 3-112 Application of remapped registers on memory access
CP15 M bit CP15 TRE bit Expected behavior
0 0 Memory accesses are controlled by the remapped default
memory attributes as defined in the ARM Architecture
Reference Manual
0 1 Memory accesses are not remapped but used the default
memory attributes
1 0 Memory accesses are not remapped and are controlled by
the MMU translation table descriptors
1 1 Memory accesses are controlled by the remapped MMU
translation table descriptors
Figure 3-51 shows the bit arrangement of the Primary Region Remap Register.
31 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved - - - - - - - - - - - -
Figure 3-51 Primary Region Remap Register format
Table 3-113 shows how the bit values correspond with the Primary Region Remap Register
functions.
Table 3-113 Primary Region Remap Register bit functions
Bits Field Function a
[31:20] - Reserved. UNP, SBZ
[19] - Remaps shareable attribute when S=1 for Normal regions b
1 = reset value
[18] - Remaps shareable attribute when S=0 for Normal regions b
0 = reset value
[17] - Remaps shareable attribute when S=1 for Device regions b
0 = reset value
[16] - Remaps shareable attribute when S= 0 for Device regions b
1= reset value
[15:14] - Remaps {TEX[0],C,B} = b111
b10 = reset value
[13:12] - Remaps {TEX[0],C,B} = b110
b00 = reset value
[11:10] - Remaps {TEX[0],C,B} = b101
b10 = reset value
[9:8] - Remaps {TEX[0],C,B} = b100
b10 = reset value
ARM DDI 0344K Copyright © 2006-2010 ARM Limited. All rights reserved. 3-101
ID060510 Non-Confidential