Cortex-A8 Technical Reference Manual - ARM Information Center

Rules for accessing the DCC
At the core side, the debug communications channel resources are:
• CP14 Debug Register c5 (DTR)
• CP14 Debug Register c1 (DSCR).
Implementations of the ARMv7 debug for the processor are so that:
Debug
• If a read of the CP14 DSCR returns 1 for the DTRRXfull flag, then a following read of
the CP14 DTR returns valid data and DTRRXfull is cleared to 0. No prefetch flush is
required between these two CP14 instructions.
• If a read of the CP14 DSCR returns 0 for the DTRRXfull flag, then a following read of
the CP14 DTR returns an Unpredictable value.
• If a read of the CP14 DSCR returns 0 for the DTRTXfull flag, then a following write to
the CP14 DTR writes the intended 32-bit word, and sets DTRTXfull to 1. No prefetch
flush is required between these two CP14 instructions.
• If a read of the CP14 DSCR returns 1 for the DTRTXfull flag, then a following write to
the CP14 DTR is Unpredictable.
When nonblocking mode is selected for DTR accesses, the following conditions are true for
memory-mapped DSCR, memory-mapped DTRRX, and DTRTX registers:
• If a read of the memory-mapped DSCR returns 0 for the DTRRXfull flag, then a following
write of the memory-mapped DTRRX passes valid data to the processor and sets
DTRRXfull to 1.
• If a read of the memory-mapped DSCR returns 1 for the DTRRXfull flag, then a following
write of the memory-mapped DTRRX is ignored, that is, both DTRRXfull and DTRRX
contents are unchanged.
• If a read of the memory-mapped DSCR returns 1 for the DTRTXfull flag, then a following
read of the memory-mapped DTRTX returns valid data and clears DTRTXfull to 0.
• If a read of the memory-mapped DSCR returns 0 for the DTRTXfull flag, then a following
read of the memory-mapped DTRTX is ignored, for example, the content of DTRTXfull
is unchanged and the read returns an Unpredictable value.
Other uses of the DCC resources are not supported by the ARMv7 debug architecture. In
particular, ARMv7 debug does not support the following:
• polling CP14 DSCR[30:29] flags to access the memory-mapped DTRRX and DTRTX
registers
• polling memory-mapped DSCR[30:29] flags to access CP14 DTR.
Note
Using the DCC in any of the nonsupported ways can be subject to race conditions.
Software access to the DCC
Software running on the processor that sends data to the debugger through the transmit channel
can use the following sequence of instructions as shown in Example 12-2.
; r0 -> word to send to the debugger
Example 12-2 Transmit data transfer (target end)
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