Cortex-A8 Technical Reference Manual - ARM Information Center

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14.2 ETM configuration Embedded Trace Macrocell ETMv3.3 permits a number of configurations. Table 14-1 shows the options implemented in the Cortex-A8 ETM. Table 14-1 ETM implementation Resource description Configuration Instruction trace Yes Data address trace Yes Data value trace No Jazelle trace - Address comparator pairs 4 Data comparators 2 Context ID comparators 1 Sequencer Yes Start/stop block Yes EmbeddedICE comparators 0 External inputs 4 External outputs 2 Extended external inputs 49 Extended external input selectors 2 Instrumentation resources 4 FIFOFULL No FIFOFULL level setting N/A Branch broadcasting Yes ASIC Control Register (bits) 8 Data suppression Yes Software access to registers Memory Readable registers Yes FIFO size 128 bytes Minimum port size 32 Maximum port size 32 Port modes Dynamic Asynchronous ATB interface Yes Load pc first No Fetch comparisons No ARM DDI 0344K Copyright © 2006-2010 ARM Limited. All rights reserved. 14-5 ID060510 Non-Confidential
14.3 ETM register summary The ETM registers are defined in the ETM Architecture Specification. Embedded Trace Macrocell Table 14-2 shows the values of the Identification registers and the Integration registers that are implementation-defined and are not described in the ETM Architecture Specification. Register name Base offset a Type Reset value Description Table 14-2 ETM register summary Configuration Code 0x004 R 0x8D294024 Configuration Code Register on page 14-8 ID 0x1E4 R 0x410CF236 ID Register on page 14-7 Configuration Code Extension 0x1E8 R 0x000008A2 Configuration Code Extension Register on page 14-9 ITMISCOUT 0xEDC W - ITMISCOUT Register on page 14-12 ITMISCIN 0xEE0 R - b ITMISCIN Register on page 14-13 ITTRIGGER 0xEE8 W - ITTRIGGER Register on page 14-13 ITATBDATA0 0xEEC W - ITATBDATA0 Register on page 14-14 ITATBCTR2 0xEF0 R - b ITATBCTR2 Register on page 14-14 ITATBCTR1 0xEF4 W - ITATBCTR1 Register on page 14-15 ITATBCTR0 0xEF8 W - ITATBCTR0 Register on page 14-15 PeripheralID4 0xFD0 R 0x00000004 Peripheral Identification Registers on page 14-10 PeripheralID5 0xFD4 R 0x00000000 PeripheralID6 0xFD8 R 0x00000000 PeripheralID7 0xFDC R 0x00000000 PeripheralID0 0xFE0 R 0x00000021 PeripheralID1 0xFE4 R 0x000000B9 PeripheralID2 0xFE8 R 0x0000006B PeripheralID3 0xFEC R 0x00000020 ComponentID0 0xFF0 R 0x0000000D Component Identification Registers on page 14-11 ComponentID1 0xFF4 R 0x00000090 ComponentID2 0xFF8 R 0x00000005 ComponentID3 0xFFC R 0x000000B1 a. The value given in the Base offset column is the address offset for memory-mapped access. To get the register number used in the ETM Architecture Specification, divide this offset by four. b. The values of these read-only registers depend on the signals on external pins of the ETM. Therefore it is not possible to define the register reset values. ARM DDI 0344K Copyright © 2006-2010 ARM Limited. All rights reserved. 14-6 ID060510 Non-Confidential
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Copyright © 2006-2010 ARM Limited.
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Web Address http://www.arm.com ARM
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Contents 2.14 The program status re
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Contents 16.6 Instruction-specific
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List of Tables Table 3-16 Debug Fea
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List of Tables Table 3-136 Secure o
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List of Tables Table 12-59 Values t
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List of Figures Cortex-A8 Technical
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List of Figures Figure 3-77 BTB arr
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List of Figures Figure 15-16 CTI Ch
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About this manual Product revision
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old Highlights interface elements,
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Feedback Feedback on the product Fe
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1.1 About the processor Introductio
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1.3 Components of the processor L1
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1.3.6 NEON 1.3.7 ETM The NEON unit
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1.5 Debug Introduction The processo
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1.7 Configurable options Table 1-1
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Introduction • The various data a
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1.9.6 r2p0-r2p1 1.9.7 r2p1-r2p2 1.9
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Chapter 2 Programmers Model This ch
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2.2 Thumb-2 instruction set Program
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Bits Field Function Programmers Mod
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2.4 Jazelle Extension 2.4.1 Jazelle
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2.5 Security Extensions architectur
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2.6 Advanced SIMD architecture Prog
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2.8 Processor operating states 2.8.
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2.10 Memory formats 2.10.1 Byte-inv
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2.12 Operating modes Programmers Mo
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System and User r0 r1 r2 r3 r4 r5 r
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2.14 The program status registers 2
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2.14.5 The GE[3:0] bits Programmers
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Mode bits Programmers Model M[4:0]
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2.15 Exceptions 2.15.1 Exception en
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2.15.5 Interrupt request 2.15.6 Abo
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This restores both the PC and the C
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2.15.13 Exception priorities Progra
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2.17 Hardware consideration for Sec
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SECMONOUT[78] instruction caches at
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Chapter 3 System Control Coprocesso
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System Control Coprocessor Register
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3.1.3 MMU control and configuration
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3.2 System control coprocessor regi
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CRn Op1 CRm Op2 Register or operati
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3.2.2 c0, Main ID Register System C
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3.2.4 c0, TCM Type Register 3.2.5 c
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3.2.7 c0, Processor Feature Registe
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• accessible in privileged modes
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System Control Coprocessor Table 3-
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Bits Field Function [11:8] L1 Harva
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Bits Field Function [11:8] Harvard
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31 28 27 24 23 20 19 16 15 12 11 8
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Table 3-30 shows the results of att
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System Control Coprocessor 31 28 27
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Table 3-36 shows the results of att
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• accessible in privileged modes
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CSSR Size 3.2.24 c0, Cache Size Sel
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System Control Coprocessor 31 30 29
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MCR p15, 0, , c1, c0, 0 ; Write Con
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Bits Field [19] Clock stop request
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Bits Field Security State NS S Tabl
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3.2.28 c1, Secure Configuration Reg
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AW EA Function Table 3-55 shows the
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3.2.32 c2, Translation Table Base R
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System Control Coprocessor Figure 3
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Bits Field Function 3.2.35 c5, Data
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3.2.36 c5, Instruction Fault Status
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3.2.38 c6, Data Fault Address Regis
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System Control Coprocessor Note •
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System Control Coprocessor Figure 3
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3.2.41 c8, TLB operations The data
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Figure 3-38 shows the bit arrangeme
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EN b 3.2.44 c9, Count Enable Clear
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EN b 3.2.46 c9, Software Increment
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EN b 3.2.48 c9, Cycle Count Registe
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EN b Table 3-96 shows the results o
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Value Description 0x44 Any cacheabl
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DBGEN || NIDEN 3.2.51 c9, User Enab
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EN 3.2.53 c9, Interrupt Enable Clea
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Figure 3-48 shows the bit arrangeme
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3.2.55 c9, L2 Cache Auxiliary Contr
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Bits Field Function [8:6] Tag RAM l
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TL bit value 3.2.57 c10, TLB preloa
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The PLE Identification and Status R
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3.2.62 c11, PLE enable commands U b
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Bits Field Function System Control
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U bit PLE bit Table 3-129 shows the
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U bit PLE bit System Control Coproc
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3.2.68 c12, Secure or Nonsecure Vec
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3.2.70 c12, Interrupt Status Regist
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The FCSE PID Register is: • a rea
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TLB CAM read/write TLB ATTR read/wr
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MCR p15 0, , c15, c3, 4 ; I-L1 TLB
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31 27 26 22 21 0 Reserved L1 Data 0
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System Control Coprocessor The L1 H
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3.2.78 c15, L1 data array operation
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Instruction L1 Data 0 register Inst
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Parity/ECC RAM read/write Data RAM
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3.2.82 c15, L2 parity/ECC array ope
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3.2.84 c15, L2 data array operation
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4.1 About unaligned and mixed-endia
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Unaligned Data and Mixed-endian Dat
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Chapter 5 Program Flow Prediction T
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5.2 Predicted instructions Program
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Program Flow Prediction Because ret
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5.4 Guidelines for optimal performa
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5.6 Operating system and predictor
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6.1 About the MMU Memory Management
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6.3 16MB supersection support Memor
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6.5 External aborts 6.5.1 External
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6.7 MMU software-accessible registe
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7.1 About the L1 memory system Leve
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7.2.6 Instruction cache maintenance
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L1 inner policy a L2 outer policy N
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7.5 Data cache features 7.5.1 Data
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7.7 Hardware support for virtual al
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Chapter 8 Level 2 Memory System Thi
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8.2 Cache organization 8.2.1 L2 cac
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8.3 Enabling and disabling the L2 c
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Level 2 Memory System Note It is en
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Level 2 Memory System Note You must
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Lock address : LockAddr Lock free :
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8.7 Parity and error correction cod
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9.1 About the external memory inter
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Integer data and CP14 writes Noncac
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9.4 AXI data read/write transaction
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Noncacheable, or strongly ordered,
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Noncacheable store word Noncacheabl
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LA Last Access External Memory Inte
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10.1 Clock domains 10.1.1 AXI clock
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10.2 Reset domains 10.2.1 Power-on
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REFCLK (PLL input) nPORESET ARESETn
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10.3 Power control 10.3.1 Dynamic p
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Clock, Reset, and Power Control the
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ATB APB I/O clamp I/O clamp L/S = L
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ATB APB I/O clamp I/O clamp LS = Le
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Clock, Reset, and Power Control 3.
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Powering up the debug and ETM domai
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7. Perform a normal software reset
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Clock, Reset, and Power Control 5.
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Chapter 11 Design for Test This cha
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In L1 MBIST Instruction Register Fi
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Note Do not test the CAMBIST arrays
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• number of rows of the L2 data,
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Design for Test Not all row setting
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In Design for Test Figure 11-4 show
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Design for Test When testing the ta
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CLK ARESETn MBISTMODE MBISTSHIFT MB
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End-of-test datalog retrieval Desig
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Pattern N RWRXMARCH 8N Row-fast Sta
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4. rscan array, data_seed = invert.
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3. R_, W, R, decr. 4. rscan data fr
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• the data after pass 1 of XADDRB
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(1 + (2 17)) 2 17 = 4,587,520 cycle
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processor input ports WEXTEST WINTE
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Design for Test toggling during shi
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12.1 Debug systems 12.1.1 Debug hos
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12.2.3 Security extensions and debu
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Instruction Mnemonic Description 12
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12.3.6 Power domains and debug 12.3
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Table 12-5 shows the APB interface
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12.4 Debug register descriptions Te
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MRC p14, 0, , c0, c0, 0 ; Read Debu
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31 30 29 28 27 26 25 24 23 22 21 20
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Bits Field Function [21:20] DTR acc
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Bits Field Function To access the D
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12.4.7 Watchpoint Fault Address Reg
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Bits Access Normal address [2] RW V
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12.4.12 Debug Run Control Register
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Table 12-23 shows how the bit value
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BVR[22:20] Meaning b011 The corresp
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Bits Field Function [15:14] Secure
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12.4.18 Operating System Lock Statu
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Debug • The sequence can be aband
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12.5 Management registers Offset Th
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Offset Register number Mnemonic Fun
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Bits Field Function [5] nDMAIRQ nDM
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12.5.7 Claim Tag Clear Register 12.
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12.5.10 Authentication Status Regis
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Table 12-45 shows fields that are i
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12.6 Debug events 12.6.1 Software d
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12.6.5 Watchpoint debug events If a
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Table 12-53 shows the values in the
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12.8 Debug state 12.8.1 Entering de
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12.8.4 Writing to the CPSR in debug
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Mode SCR[0] For CP15 instructions,
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Page 395 and 396: 12.9.3 Cache usage profiling Debug
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Page 405 and 406: Debug Table 12-59 Values to write t
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Page 411 and 412: Writing the CPSR in debug state Exa
Page 413 and 414: Debug Example 12-21 Reading a word
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Page 417 and 418: 12.12 Debugging systems with energy
Page 419 and 420: MOV r0, r4 POP {r4, pc} Example 12-
Page 421 and 422: Chapter 13 NEON and VFP Programmers
Page 423 and 424: 13.2 General-purpose registers 13.2
Page 425 and 426: 13.3 Short vectors 13.3.1 About reg
Page 427 and 428: 13.3.2 Operations using register ba
Page 429 and 430: NEON and VFP Programmers Model The
Page 431 and 432: Note All hardware ID information is
Page 433 and 434: Bits Field Function [12:8] - Reserv
Page 435 and 436: NEON and VFP Programmers Model Tabl
Page 437 and 438: 13.6 Compliance with the IEEE 754 s
Page 439 and 440: Underflow NEON and VFP Programmers
Page 441 and 442: 14.1 About the ETM 14.1.1 ETM featu
Page 443: 14.1.3 NEON Bridge and bus matrix A
Page 447 and 448: Bits Field Function [11:8] Major ET
Page 449 and 450: 14.4.4 Peripheral Identification Re
Page 451 and 452: See the ETM Architecture Specificat
Page 453 and 454: Embedded Trace Macrocell Table 14-1
Page 457 and 458: 14.5.3 Enabling events 14.5.4 Addre
Page 459 and 460: 14.7 Context ID tracing Embedded Tr
Page 461 and 462: 14.9 Idle state control Embedded Tr
Page 465 and 466: Chapter 15 Cross Trigger Interface
Page 467 and 468: CTICHIN[0] CTICHIN[1] CTICHIN[2] CT
Page 469 and 470: 15.2 Trigger inputs and outputs Tri
Page 471 and 472: 15.3 Connecting asynchronous channe
Page 473 and 474: 15.5 CTI register summary Address o
Page 475 and 476: 15.6 CTI register descriptions This
Page 477 and 478: 15.6.4 CTI Application Trigger Clea
Page 479 and 480: Table 15-10 shows how the bit value
Page 481 and 482: 15.6.12 ASIC Control Register, ASIC
Page 483 and 484: 15.7 CTI Integration Test Registers
Page 485 and 486: 15.7.4 ITTRIGOUTACK, 0xEF0 15.7.5 I
Page 487 and 488: Cross Trigger Interface Table 15-26
Page 489 and 490: 15.8.3 Device Type Identifier, 0xFC
Page 491 and 492: Cross Trigger Interface Table 15-31
Page 493 and 494: 16.1 About instruction cycle timing
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Instruction Cycle Timing Example 16
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Table 16-4 shows the operation of m
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Table 16-9 shows the operation of l
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d. See Load/store instructions on p
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Instruction Cycle Timing Table 16-1
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16.4 Other pipeline-dependent laten
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16.4.5 Conditional instructions Ins
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16.6 Instruction-specific schedulin
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Instruction Cycle Timing VNEG Dd,Dm
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VMLA a VMLS a VMLAa VMLSa VQDMLAa V
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VSLI VSRI 16.6.5 Advanced SIMD floa
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16.6.6 Advanced SIMD byte permute i
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Instruction Table 16-23 shows the o
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Instruction VST3 3-reg (unaligned)
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Instruction VLD3 3-reg (unaligned)
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Instruction Single precision cycles
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• FMACS, FNMACS • FMSCS, FNMSCS
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is dual issued with previous instru
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17.1 About setup and hold times AC
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17.2 AXI interface Table 17-2 shows
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17.3 ATB and CTI interfaces Table 1
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AC Characteristics Table 17-4 Timin
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17.6 L2 preload interface AC Charac
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17.8 Miscellaneous signals AC Chara
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A.1 AXI interface Signal Descriptio
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A.3 MBIST and DFT interface A.3.1 M
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A.4 Preload engine interface Table
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A.6 Miscellaneous signals Table A-7
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Signal I/O Reset Description CFGNMF
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Signal I/O Reset Description DBGNOP
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Appendix B Instruction Mnemonics Th
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Instruction Mnemonics Table B-1 Adv
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Appendix C Revisions This appendix
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Revisions Added text to clarify des
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Glossary This glossary describes so
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Glossary Automatic Test Pattern Gen
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Big-endian memory Memory in which:
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Conditional execution Glossary incl
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Glossary Embedded Trace Macrocell (
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Illegal instruction An instruction
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Glossary NaN Not a number. A symbol
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Glossary Significand The component
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Glossary Watchpoint A watchpoint is
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